Enums and type definitions for communication interfaces.

Enums and type definitions for communication interfaces.

SPI Protocol

TMC51x0 uses 40-bit SPI datagrams per datasheet section 4.1:

• Datagram structure: 8-bit address + 32-bit data = 40 bits (5 bytes)
• Bit positions: bit 39 (MSB, transmitted first) ... bit 0 (LSB, transmitted last)
• Bit 39: W (WRITE_notREAD bit) - 0 for read, 1 for write
• Bits 38-32: 7-bit register address
• Bits 31-0: 32-bit data (right-aligned)

Byte structure (MSB transmitted first):

• Byte 0: W bit (bit 7) + 7-bit address (bits 6-0)
  • Read access: bit 7 = 0, address in bits 6-0
  • Write access: bit 7 = 1, address in bits 6-0 (add 0x80 to address)
• Bytes 1-4: 32-bit data (MSB-first, right-aligned)
• Bytes 5-7: Unused (optional, can be used for daisy-chaining multiple chips)

Response structure (40 bits):

• Byte 0: SPI_STATUS (8 bits, bits 39-32) - Status flags
• Bytes 1-4: 32-bit data (bits 31-0, MSB-first)

Read access behavior (pipelined):

• First transfer: Send address with dummy data, receive dummy response
• Second transfer: Send address again, receive actual data from previous read

Write access behavior:

• Send address | 0x80, then 4 bytes of data
• Response contains SPI_STATUS + previously written data

SPI Mode: Mode 3 (CPOL=1, CPHA=1) Clock: MSB-first Minimum: 40 SCK clock cycles required CSN: Must stay low during entire transaction

UART Protocol

TMC51x0 uses UART single wire interface per datasheet section 5.1. Each byte is transmitted LSB...MSB, highest byte transmitted first.

Write Access Datagram (64 bits = 8 bytes total):

• Byte 0: Sync nibble (0x05 = 1,0,1,0) + Reserved (0)
• Byte 1: NODEADDR (8-bit node address, 0-254)
• Byte 2: RW bit (bit 7 = 1 for write) + 7-bit register address
• Bytes 3-6: 32-bit data (high byte to low byte, MSB-first)
• Byte 7: CRC8 checksum (calculated over bytes 0-6)

Read Access Request Datagram (32 bits = 4 bytes total):

• Byte 0: Sync nibble (0x05) + Reserved (0)
• Byte 1: NODEADDR (8-bit node address)
• Byte 2: RW bit (bit 7 = 0 for read) + 7-bit register address
• Byte 3: CRC8 checksum (calculated over bytes 0-2)

Read Access Reply Datagram (64 bits = 8 bytes total):

• Byte 0: Sync nibble (0x05) + Reserved (0)
• Byte 1: Master Address (0xFF)
• Byte 2: Register Address (0x00)
• Bytes 3-6: 32-bit data (high byte to low byte, MSB-first)
• Byte 7: CRC8 checksum (calculated over bytes 0-6)

CRC8: CRC8-ATM polynomial (0x07), applied LSB to MSB.

Baud Rate:

• Minimum: 9000 baud
• Maximum: fCLK/16
• Baud rate is automatically detected from sync frame timing

Communication Reset:

• Pause time > 63 bit times between start bits resets communication
• Recovery time: 12 bit times of bus idle time

SENDDELAY:

• Programmable delay time after read request before reply
• Default: 8 bit times
• Multi-node systems: Set SENDDELAY to min. 2 for all nodes