Enums and type definitions for communication interfaces.

For parameter read/write access, either UART or SPI may be used. Both interfaces share the same TMCL command structure and follow a strict command/reply order.

SPI Command Format

Table 3: Command format for parameter read/write access through SPI

BYTE	0	1-2	3	4-6	7
Bits	0-7	8-19	20-23	24-55	56-63
Desc	Operation	Type	Motor/Bank	Data	Checksum

SPI Reply Format

Table 4: Reply format for parameter read/write access through SPI

BYTE	0	1	2	3-6	7
Bits	0-7	8-15	16-23	24-55	56-63
Desc	SPI Status	TMCL Status	Operation	Data	Checksum

UART Command Format

BYTE	0	1	2-3	4	5-8	9
Desc	Sync+Address	Command	Type	Motor/Bank	Data	Checksum

UART Reply Format

BYTE	0	1	2	3	4-7	8
Desc	Host Address	Sync+Address	TMCL Status	Operation	Data	Checksum

GPIO Control Interface

The TMC9660 provides several GPIO pins for system control and status monitoring. The interface uses board-agnostic naming and signal levels to accommodate different board implementations (direct connection, inverters, etc.).

Control Pins (Output from Host)

RST (Pin 22): External System Reset Input
- Device remains in reset while this pin is in its active state
- Has internal pull-down resistor
- Active level depends on board implementation (configure via set_pin_active_level)
DRV_EN (Pin 21): Driver Enable Input
- Enables the motor driver outputs
- Has internal pull-down resistor
- Active level depends on board implementation (configure via set_pin_active_level)
WAKE (Pin 19): Wake Input
- Drive to active state to enable power-up and exit from hibernation mode
- When not shorted to VSA, external pull-down resistor recommended
- Active level depends on board implementation (configure via set_pin_active_level)

Status Pins (Input to Host)

FAULTN (Pin 20): FAULT Output Signal (open drain)
- Indicates busy state during bootstrapping or severe error
- Active level depends on board implementation (configure via set_pin_active_level)
- Use gpioRead(TMC9660CtrlPin::FAULTN, signal) to check fault status