Advanced ESP32-integrated I2C controller for ESP-IDF v5.5+ with proper bus-device architecture.
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Advanced ESP32-integrated I2C controller for ESP-IDF v5.5+ with proper bus-device architecture.
This header provides a comprehensive I2C implementation that properly utilizes the ESP-IDF v5.5+ bus-device model, following the same pattern as the SPI implementation. The architecture separates bus management from device operations, providing clean abstraction and optimal resource management.
ESP32C6/ESP-IDF v5.5+ Features Supported:
- Bus-Device Architecture: Separate EspI2cBus and EspI2cDevice classes
- Modern API: Uses i2c_new_master_bus() and i2c_master_bus_add_device()
- Mode-Aware Operations: Single mode variable determines sync vs async capabilities
- Per-Device Configuration: Each device has its own clock speed and settings
- Thread Safety: Full RTOS integration with proper synchronization
- Device Management: Dynamic device addition/removal with proper cleanup
- BaseI2c Integration: EspI2cDevice inherits from BaseI2c for portability
- Comprehensive Error Handling: Proper error conversion and reporting
- Resource Management: Automatic cleanup and proper resource lifecycle
Performance Characteristics:
- Standard Mode: 100 kHz
- Fast Mode: 400 kHz
- Fast Mode Plus: 1 MHz (ESP32C6)
- 7-bit and 10-bit addressing support
- Clock stretching with configurable timeout
- Hardware FIFO utilization
- Multi-master operation capability
- Author
- Nebiyu Tadesse
- Date
- 2025
- Copyright
- HardFOC
- Version
- 4.0.0 - Mode-aware architecture with DRY implementation
- Note
- This implementation requires ESP-IDF v5.5+ and is optimized for ESP32C6.
-
Thread-safe operation is guaranteed for all public methods.
-
Follows the same architectural pattern as EspSpi for consistency.
-
ESP-IDF v5.5+ enforces strict separation between sync/async modes.
if (!i2c_bus.Initialize()) {
}
int device_index = i2c_bus.CreateDevice(device_config);
BaseI2c* device = i2c_bus.GetDevice(device_index);
uint8_t data[] = {0x10, 0x20, 0x30};
hf_i2c_err_t
Definition BaseI2c.h:85
@ HF_I2C_MODE_SYNC
Sync mode: blocking operations only, no queue.
@ HF_I2C_ADDR_7_BIT
7-bit address
Abstract base class for I2C device implementations.
Definition BaseI2c.h:196
virtual hf_i2c_err_t Write(const hf_u8_t *data, hf_u16_t length, hf_u32_t timeout_ms=0) noexcept=0
Write data to the I2C device.
Manages a single I2C bus. Handles bus initialization and device creation.
Definition EspI2c.h:548
I2C device configuration structure.
Definition EspTypes_I2C.h:225
uint16_t device_address
7-bit or 10-bit device address
Definition EspTypes_I2C.h:226
hf_i2c_address_bits_t dev_addr_length
Address bit length (7 or 10 bit)
Definition EspTypes_I2C.h:227
uint32_t scl_speed_hz
SCL clock frequency for this device.
Definition EspTypes_I2C.h:228
I2C master bus configuration structure.
Definition EspTypes_I2C.h:195
hf_pin_num_t sda_io_num
SDA GPIO pin number.
Definition EspTypes_I2C.h:197
uint32_t trans_queue_depth
Transaction queue depth for async ops.
Definition EspTypes_I2C.h:200
i2c_port_t i2c_port
I2C port number (0 to MAX_PORTS-1)
Definition EspTypes_I2C.h:196
hf_pin_num_t scl_io_num
SCL GPIO pin number.
Definition EspTypes_I2C.h:198
hf_i2c_mode_t mode
Operation mode (sync/async)
Definition EspTypes_I2C.h:199
if (!i2c_bus.Initialize()) {
}
int device_index = i2c_bus.CreateDevice(device_config);
BaseI2c* device = i2c_bus.GetDevice(device_index);
uint8_t data[] = {0x10, 0x20, 0x30};
hf_i2c_err_t result = device->WriteAsync(data,
sizeof(data),
});
constexpr std::string_view HfI2CErrToString(hf_i2c_err_t err) noexcept
Convert hf_i2c_err_t to human-readable string.
Definition BaseI2c.h:96
@ HF_I2C_MODE_ASYNC
Async mode: non-blocking operations only, with queue.