max22200_registers.hpp

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#pragma once
#include <cstdint>
 
namespace max22200 {
 
constexpr uint8_t NUM_CHANNELS_ = 8;
 
constexpr uint32_t MAX_SPI_FREQ_STANDALONE_ = 10000000; // 10 MHz
 
constexpr uint32_t MAX_SPI_FREQ_DAISY_CHAIN_ = 5000000; // 5 MHz
 
// ============================================================================
// Register Bank Addresses (A_BNK field in Command Register, bits [4:1])
// ============================================================================
 
namespace RegBank {
constexpr uint8_t STATUS   = 0x00; 
constexpr uint8_t CFG_CH0  = 0x01; 
constexpr uint8_t CFG_CH1  = 0x02; 
constexpr uint8_t CFG_CH2  = 0x03; 
constexpr uint8_t CFG_CH3  = 0x04; 
constexpr uint8_t CFG_CH4  = 0x05; 
constexpr uint8_t CFG_CH5  = 0x06; 
constexpr uint8_t CFG_CH6  = 0x07; 
constexpr uint8_t CFG_CH7  = 0x08; 
constexpr uint8_t FAULT    = 0x09; 
constexpr uint8_t CFG_DPM  = 0x0A; 
} // namespace RegBank
 
// ============================================================================
// Command Register (8-bit, Write Only)
// ============================================================================
 
namespace CommandReg {
constexpr uint8_t RBW_POS       = 7;    
constexpr uint8_t RBW_READ      = 0x00; 
constexpr uint8_t RBW_WRITE     = 0x80; 
 
constexpr uint8_t A_BNK_POS     = 1;    
constexpr uint8_t A_BNK_MASK    = 0x1E; 
 
constexpr uint8_t MODE_8BIT     = 0x01; 
constexpr uint8_t MODE_32BIT    = 0x00; 
 
constexpr uint8_t build(uint8_t bank, bool write, bool mode8 = false) {
  return static_cast<uint8_t>(
      (write ? RBW_WRITE : RBW_READ) |
      ((bank & 0x0F) << A_BNK_POS) |
      (mode8 ? MODE_8BIT : MODE_32BIT));
}
} // namespace CommandReg
 
// ============================================================================
// STATUS Register (0x00) — 32-bit
// ============================================================================
 
namespace StatusReg {
// Byte 3 (bits 31:24) — Channel activation
constexpr uint32_t ONCH_SHIFT    = 24;   
constexpr uint32_t ONCH_MASK     = 0xFF000000u; 
 
// Byte 2 (bits 23:16) — Fault masks + FREQM
constexpr uint32_t M_OVT_BIT     = (1u << 23); 
constexpr uint32_t M_OCP_BIT     = (1u << 22); 
constexpr uint32_t M_OLF_BIT     = (1u << 21); 
constexpr uint32_t M_HHF_BIT     = (1u << 20); 
constexpr uint32_t M_DPM_BIT     = (1u << 19); 
constexpr uint32_t M_COMF_BIT    = (1u << 18); 
constexpr uint32_t M_UVM_BIT     = (1u << 17); 
constexpr uint32_t FREQM_BIT     = (1u << 16); 
 
// Byte 1 (bits 15:8) — Channel-pair mode configuration
constexpr uint32_t CM76_SHIFT    = 14;   
constexpr uint32_t CM76_MASK     = (0x03u << 14); 
constexpr uint32_t CM54_SHIFT    = 12;   
constexpr uint32_t CM54_MASK     = (0x03u << 12); 
constexpr uint32_t CM32_SHIFT    = 10;   
constexpr uint32_t CM32_MASK     = (0x03u << 10); 
constexpr uint32_t CM10_SHIFT    = 8;    
constexpr uint32_t CM10_MASK     = (0x03u << 8);  
 
// Byte 0 (bits 7:0) — Fault flags (read-only except ACTIVE)
constexpr uint32_t OVT_BIT       = (1u << 7);  
constexpr uint32_t OCP_BIT       = (1u << 6);  
constexpr uint32_t OLF_BIT       = (1u << 5);  
constexpr uint32_t HHF_BIT       = (1u << 4);  
constexpr uint32_t DPM_BIT       = (1u << 3);  
constexpr uint32_t COMER_BIT     = (1u << 2);  
constexpr uint8_t FAULT_BYTE_COMER = 0x04u;
constexpr uint32_t UVM_BIT       = (1u << 1);  
constexpr uint32_t ACTIVE_BIT    = (1u << 0);  
 
constexpr uint32_t FAULT_FLAGS_MASK = 0xFEu;
 
constexpr uint8_t CM_INDEPENDENT = 0x00;
constexpr uint8_t CM_PARALLEL    = 0x01;
constexpr uint8_t CM_HBRIDGE     = 0x02;
constexpr uint8_t CM_RESERVED    = 0x03;
} // namespace StatusReg
 
// ============================================================================
// Channel Configuration Register (CFG_CHx, 0x01-0x08) — 32-bit
// ============================================================================
 
namespace CfgChReg {
// Bit 31: HFS (Half Full-Scale)
constexpr uint32_t HFS_BIT       = (1u << 31); 
 
// Bits 30:24: HOLD current (7-bit)
constexpr uint32_t HOLD_SHIFT    = 24;   
constexpr uint32_t HOLD_MASK     = (0x7Fu << 24); 
 
// Bit 23: TRGnSPI (Trigger source)
constexpr uint32_t TRGNSPI_BIT   = (1u << 23); 
 
// Bits 22:16: HIT current (7-bit)
constexpr uint32_t HIT_SHIFT     = 16;   
constexpr uint32_t HIT_MASK      = (0x7Fu << 16); 
 
// Bits 15:8: HIT time (8-bit)
constexpr uint32_t HITT_SHIFT    = 8;    
constexpr uint32_t HITT_MASK     = (0xFFu << 8); 
 
// Bit 7: VDRnCDR (Drive mode)
constexpr uint32_t VDRNCDR_BIT   = (1u << 7);   
 
// Bit 6: HSnLS (High-side/Low-side)
constexpr uint32_t HSNLS_BIT     = (1u << 6);   
 
// Bits 5:4: FREQ_CFG (Chopping frequency)
constexpr uint32_t FREQ_CFG_SHIFT = 4;   
constexpr uint32_t FREQ_CFG_MASK  = (0x03u << 4); 
 
// Bit 3: SRC (Slew rate control)
constexpr uint32_t SRC_BIT       = (1u << 3);   
 
// Bit 2: OL_EN (Open load detect enable)
constexpr uint32_t OL_EN_BIT     = (1u << 2);   
 
// Bit 1: DPM_EN (DPM detection enable)
constexpr uint32_t DPM_EN_BIT    = (1u << 1);   
 
// Bit 0: HHF_EN (HIT current check enable)
constexpr uint32_t HHF_EN_BIT    = (1u << 0);   
 
constexpr uint8_t MAX_HOLD       = 127;
constexpr uint8_t MAX_HIT        = 127;
constexpr uint8_t MAX_HIT_TIME   = 255;
constexpr uint8_t CONTINUOUS_HIT = 255;
} // namespace CfgChReg
 
// ============================================================================
// FAULT Register (0x09) — 32-bit, Read Only
// ============================================================================
 
namespace FaultReg {
constexpr uint32_t OCP_SHIFT = 24;   
constexpr uint32_t OCP_MASK  = 0xFF000000u; 
constexpr uint32_t HHF_SHIFT = 16;   
constexpr uint32_t HHF_MASK  = 0x00FF0000u; 
constexpr uint32_t OLF_SHIFT = 8;    
constexpr uint32_t OLF_MASK  = 0x0000FF00u; 
constexpr uint32_t DPM_SHIFT = 0;    
constexpr uint32_t DPM_MASK  = 0x000000FFu; 
} // namespace FaultReg
 
// ============================================================================
// CFG_DPM Register (0x0A) — 32-bit, DPM Algorithm Configuration
// ============================================================================
 
namespace CfgDpmReg {
constexpr uint32_t DPM_ISTART_SHIFT = 8;   
constexpr uint32_t DPM_ISTART_MASK  = (0x7Fu << 8); 
constexpr uint32_t DPM_TDEB_SHIFT   = 4;    
constexpr uint32_t DPM_TDEB_MASK    = (0x0Fu << 4); 
constexpr uint32_t DPM_IPTH_SHIFT   = 0;    
constexpr uint32_t DPM_IPTH_MASK    = 0x0Fu; 
} // namespace CfgDpmReg
 
// ============================================================================
// Helper functions
// ============================================================================
 
constexpr uint8_t getChannelCfgBank(uint8_t channel) {
  return static_cast<uint8_t>(RegBank::CFG_CH0 + channel);
}
 
// Forward declarations
enum class DriveMode : uint8_t;
enum class ChannelMode : uint8_t;
 
} // namespace max22200