max22200_registers.hpp File Reference

Register definitions and constants for MAX22200 IC. More...

#include <cstdint>

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Namespaces
namespace	max22200
namespace	max22200::RegBank
	Register bank addresses for MAX22200.
namespace	max22200::CommandReg
	Command Register bit field definitions and helper functions.
namespace	max22200::StatusReg
	STATUS register bit field definitions.
namespace	max22200::CfgChReg
	Channel configuration register bit field definitions.
namespace	max22200::FaultReg
	FAULT register bit field definitions.
namespace	max22200::CfgDpmReg
	CFG_DPM register bit field definitions.

Functions
constexpr uint8_t	max22200::CommandReg::build (uint8_t bank, bool write, bool mode8=false)
constexpr uint8_t	max22200::getChannelCfgBank (uint8_t channel)

Variables
constexpr uint8_t	max22200::NUM_CHANNELS_ = 8
	Number of channels on the MAX22200.
constexpr uint32_t	max22200::MAX_SPI_FREQ_STANDALONE_ = 10000000
	Maximum SPI clock frequency without daisy chaining (Hz)
constexpr uint32_t	max22200::MAX_SPI_FREQ_DAISY_CHAIN_ = 5000000
	Maximum SPI clock frequency with daisy chaining (Hz)
constexpr uint8_t	max22200::RegBank::STATUS = 0x00
	Status register (32-bit) — channel on/off, HW config, faults, ACTIVE.
constexpr uint8_t	max22200::RegBank::CFG_CH0 = 0x01
	Channel 0 configuration register (32-bit)
constexpr uint8_t	max22200::RegBank::CFG_CH1 = 0x02
	Channel 1 configuration register (32-bit)
constexpr uint8_t	max22200::RegBank::CFG_CH2 = 0x03
	Channel 2 configuration register (32-bit)
constexpr uint8_t	max22200::RegBank::CFG_CH3 = 0x04
	Channel 3 configuration register (32-bit)
constexpr uint8_t	max22200::RegBank::CFG_CH4 = 0x05
	Channel 4 configuration register (32-bit)
constexpr uint8_t	max22200::RegBank::CFG_CH5 = 0x06
	Channel 5 configuration register (32-bit)
constexpr uint8_t	max22200::RegBank::CFG_CH6 = 0x07
	Channel 6 configuration register (32-bit)
constexpr uint8_t	max22200::RegBank::CFG_CH7 = 0x08
	Channel 7 configuration register (32-bit)
constexpr uint8_t	max22200::RegBank::FAULT = 0x09
	Fault register (32-bit, read-only) — per-channel fault flags.
constexpr uint8_t	max22200::RegBank::CFG_DPM = 0x0A
	DPM configuration register (32-bit) — global DPM algorithm settings.
constexpr uint8_t	max22200::CommandReg::RBW_POS = 7
	Read/Write bit position.
constexpr uint8_t	max22200::CommandReg::RBW_READ = 0x00
	Read operation (bit 7 = 0)
constexpr uint8_t	max22200::CommandReg::RBW_WRITE = 0x80
	Write operation (bit 7 = 1)
constexpr uint8_t	max22200::CommandReg::A_BNK_POS = 1
	Bank address bit position (bits 4:1)
constexpr uint8_t	max22200::CommandReg::A_BNK_MASK = 0x1E
	Bank address mask (bits 4:1)
constexpr uint8_t	max22200::CommandReg::MODE_8BIT = 0x01
	8-bit MSB only access (bit 0 = 1)
constexpr uint8_t	max22200::CommandReg::MODE_32BIT = 0x00
	32-bit full access (bit 0 = 0)
constexpr uint32_t	max22200::StatusReg::ONCH_SHIFT = 24
	ONCH bit shift (bits 31:24)
constexpr uint32_t	max22200::StatusReg::ONCH_MASK = 0xFF000000u
	ONCH bitmask.
constexpr uint32_t	max22200::StatusReg::M_OVT_BIT = (1u << 23)
	OVT fault mask (1=masked, 0=signaled)
constexpr uint32_t	max22200::StatusReg::M_OCP_BIT = (1u << 22)
	OCP fault mask.
constexpr uint32_t	max22200::StatusReg::M_OLF_BIT = (1u << 21)
	OLF fault mask.
constexpr uint32_t	max22200::StatusReg::M_HHF_BIT = (1u << 20)
	HHF fault mask.
constexpr uint32_t	max22200::StatusReg::M_DPM_BIT = (1u << 19)
	DPM fault mask.
constexpr uint32_t	max22200::StatusReg::M_COMF_BIT = (1u << 18)
	Communication fault mask (reset value = 1, masked by default)
constexpr uint32_t	max22200::StatusReg::M_UVM_BIT = (1u << 17)
	UVM fault mask.
constexpr uint32_t	max22200::StatusReg::FREQM_BIT = (1u << 16)
	Master frequency (0=100kHz, 1=80kHz)
constexpr uint32_t	max22200::StatusReg::CM76_SHIFT = 14
	CM76 bit shift (bits 15:14)
constexpr uint32_t	max22200::StatusReg::CM76_MASK = (0x03u << 14)
	CM76 bitmask.
constexpr uint32_t	max22200::StatusReg::CM54_SHIFT = 12
	CM54 bit shift (bits 13:12)
constexpr uint32_t	max22200::StatusReg::CM54_MASK = (0x03u << 12)
	CM54 bitmask.
constexpr uint32_t	max22200::StatusReg::CM32_SHIFT = 10
	CM32 bit shift (bits 11:10)
constexpr uint32_t	max22200::StatusReg::CM32_MASK = (0x03u << 10)
	CM32 bitmask.
constexpr uint32_t	max22200::StatusReg::CM10_SHIFT = 8
	CM10 bit shift (bits 9:8)
constexpr uint32_t	max22200::StatusReg::CM10_MASK = (0x03u << 8)
	CM10 bitmask.
constexpr uint32_t	max22200::StatusReg::OVT_BIT = (1u << 7)
	Overtemperature fault flag (read-only)
constexpr uint32_t	max22200::StatusReg::OCP_BIT = (1u << 6)
	Overcurrent fault flag (read-only)
constexpr uint32_t	max22200::StatusReg::OLF_BIT = (1u << 5)
	Open-load fault flag (read-only)
constexpr uint32_t	max22200::StatusReg::HHF_BIT = (1u << 4)
	HIT current not reached flag (read-only)
constexpr uint32_t	max22200::StatusReg::DPM_BIT = (1u << 3)
	Plunger movement detection flag (read-only)
constexpr uint32_t	max22200::StatusReg::COMER_BIT = (1u << 2)
constexpr uint8_t	max22200::StatusReg::FAULT_BYTE_COMER = 0x04u
	Fault byte value returned on SDO when COMER is set (per datasheet Figure 6)
constexpr uint32_t	max22200::StatusReg::UVM_BIT = (1u << 1)
	Undervoltage flag (read-only, set at POR, cleared by read)
constexpr uint32_t	max22200::StatusReg::ACTIVE_BIT = (1u << 0)
	Global enable bit (write: 0=low-power, 1=normal operation)
constexpr uint32_t	max22200::StatusReg::FAULT_FLAGS_MASK = 0xFEu
	Fault flags byte mask (bits 7:1, read-only)
constexpr uint8_t	max22200::StatusReg::CM_INDEPENDENT = 0x00
	Channel-pair mode: independent operation.
constexpr uint8_t	max22200::StatusReg::CM_PARALLEL = 0x01
	Channel-pair mode: parallel mode (double current)
constexpr uint8_t	max22200::StatusReg::CM_HBRIDGE = 0x02
	Channel-pair mode: H-bridge mode (full-bridge)
constexpr uint8_t	max22200::StatusReg::CM_RESERVED = 0x03
	Channel-pair mode: reserved (do not use)
constexpr uint32_t	max22200::CfgChReg::HFS_BIT = (1u << 31)
	HFS bit (0=1x full-scale, 1=0.5x half-scale)
constexpr uint32_t	max22200::CfgChReg::HOLD_SHIFT = 24
	HOLD current bit shift.
constexpr uint32_t	max22200::CfgChReg::HOLD_MASK = (0x7Fu << 24)
	HOLD current mask (7-bit, 0-127)
constexpr uint32_t	max22200::CfgChReg::TRGNSPI_BIT = (1u << 23)
	TRGnSPI bit (0=SPI ONCH, 1=TRIG pin)
constexpr uint32_t	max22200::CfgChReg::HIT_SHIFT = 16
	HIT current bit shift.
constexpr uint32_t	max22200::CfgChReg::HIT_MASK = (0x7Fu << 16)
	HIT current mask (7-bit, 0-127)
constexpr uint32_t	max22200::CfgChReg::HITT_SHIFT = 8
	HIT time bit shift.
constexpr uint32_t	max22200::CfgChReg::HITT_MASK = (0xFFu << 8)
	HIT time mask (8-bit, 0-255)
constexpr uint32_t	max22200::CfgChReg::VDRNCDR_BIT = (1u << 7)
	VDRnCDR bit (0=CDR, 1=VDR)
constexpr uint32_t	max22200::CfgChReg::HSNLS_BIT = (1u << 6)
	HSnLS bit (0=low-side, 1=high-side)
constexpr uint32_t	max22200::CfgChReg::FREQ_CFG_SHIFT = 4
	FREQ_CFG bit shift.
constexpr uint32_t	max22200::CfgChReg::FREQ_CFG_MASK = (0x03u << 4)
	FREQ_CFG mask (2-bit)
constexpr uint32_t	max22200::CfgChReg::SRC_BIT = (1u << 3)
	SRC bit (0=fast, 1=slew-rate controlled)
constexpr uint32_t	max22200::CfgChReg::OL_EN_BIT = (1u << 2)
	OL_EN bit (0=disabled, 1=enabled)
constexpr uint32_t	max22200::CfgChReg::DPM_EN_BIT = (1u << 1)
	DPM_EN bit (0=disabled, 1=enabled)
constexpr uint32_t	max22200::CfgChReg::HHF_EN_BIT = (1u << 0)
	HHF_EN bit (0=disabled, 1=enabled)
constexpr uint8_t	max22200::CfgChReg::MAX_HOLD = 127
	Maximum HOLD current register value (7-bit)
constexpr uint8_t	max22200::CfgChReg::MAX_HIT = 127
	Maximum HIT current register value (7-bit)
constexpr uint8_t	max22200::CfgChReg::MAX_HIT_TIME = 255
	Maximum HIT time register value (8-bit)
constexpr uint8_t	max22200::CfgChReg::CONTINUOUS_HIT = 255
	HIT time value for continuous IHIT (tHIT = ∞)
constexpr uint32_t	max22200::FaultReg::OCP_SHIFT = 24
	OCP bit shift (bits 31:24)
constexpr uint32_t	max22200::FaultReg::OCP_MASK = 0xFF000000u
	OCP bitmask.
constexpr uint32_t	max22200::FaultReg::HHF_SHIFT = 16
	HHF bit shift (bits 23:16)
constexpr uint32_t	max22200::FaultReg::HHF_MASK = 0x00FF0000u
	HHF bitmask.
constexpr uint32_t	max22200::FaultReg::OLF_SHIFT = 8
	OLF bit shift (bits 15:8)
constexpr uint32_t	max22200::FaultReg::OLF_MASK = 0x0000FF00u
	OLF bitmask.
constexpr uint32_t	max22200::FaultReg::DPM_SHIFT = 0
	DPM bit shift (bits 7:0)
constexpr uint32_t	max22200::FaultReg::DPM_MASK = 0x000000FFu
	DPM bitmask.
constexpr uint32_t	max22200::CfgDpmReg::DPM_ISTART_SHIFT = 8
	DPM_ISTART bit shift (bits 14:8)
constexpr uint32_t	max22200::CfgDpmReg::DPM_ISTART_MASK = (0x7Fu << 8)
	DPM_ISTART mask (7-bit)
constexpr uint32_t	max22200::CfgDpmReg::DPM_TDEB_SHIFT = 4
	DPM_TDEB bit shift (bits 7:4)
constexpr uint32_t	max22200::CfgDpmReg::DPM_TDEB_MASK = (0x0Fu << 4)
	DPM_TDEB mask (4-bit)
constexpr uint32_t	max22200::CfgDpmReg::DPM_IPTH_SHIFT = 0
	DPM_IPTH bit shift (bits 3:0)
constexpr uint32_t	max22200::CfgDpmReg::DPM_IPTH_MASK = 0x0Fu
	DPM_IPTH mask (4-bit)

Detailed Description

Register definitions and constants for MAX22200 IC.

This file defines the register map, bit fields, and helper functions for the MAX22200 octal solenoid and motor driver IC.

MAX22200 Register Architecture

The MAX22200 uses a two-phase SPI protocol:

• Phase 1: Write 8-bit Command Register (CMD pin HIGH)
• Phase 2: Read/Write data register (CMD pin LOW), 8 or 32 bits

Register Map

The MAX22200 has 10x 32-bit data registers plus one 8-bit Command Register:

A_BNK	Register	Size	Description
0x00	STATUS	32-bit	Channel on/off, HW config, fault flags, ACTIVE
0x01	CFG_CH0	32-bit	Channel 0 configuration (all params)
0x02	CFG_CH1	32-bit	Channel 1 configuration
0x03	CFG_CH2	32-bit	Channel 2 configuration
0x04	CFG_CH3	32-bit	Channel 3 configuration
0x05	CFG_CH4	32-bit	Channel 4 configuration
0x06	CFG_CH5	32-bit	Channel 5 configuration
0x07	CFG_CH6	32-bit	Channel 6 configuration
0x08	CFG_CH7	32-bit	Channel 7 configuration
0x09	FAULT	32-bit	Per-channel fault flags (OCP/HHF/OLF/DPM)
0x0A	CFG_DPM	32-bit	DPM algorithm configuration (global)

Command Register Protocol

The Command Register (8-bit, write-only) must be written first before any register access. It is written with CMD pin HIGH. The device responds with STATUS[7:0] (Fault Flag Byte) on SDO during the Command Register write.

Command Register bit layout:

• Bit 7: RB/W (0=Read, 1=Write)
• Bits 6:5: RFU (Reserved, write 0)
• Bits 4:1: A_BNK (Register bank address, 0x00-0x0A)
• Bit 0: 8bit/n32bits (1=8-bit MSB only, 0=32-bit full)

After writing the Command Register, set CMD pin LOW and perform the data transfer (1 byte for 8-bit mode, 4 bytes for 32-bit mode).

Note

Per MAX22200 datasheet Rev 1 (3/25), Document 19-100531

Copyright

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