TLE92466ED_Registers.hpp

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#ifndef TLE92466ED_REGISTERS_HPP
#define TLE92466ED_REGISTERS_HPP
 
#include <cstdint>
 
namespace TLE92466ED {
 
//==============================================================================
// SPI FRAME STRUCTURES (32-BIT)
//==============================================================================
 
union SPIFrame {
    uint32_t word;          
    
    struct {
        uint32_t data : 16;      
        uint32_t rw : 1;         
        uint32_t address : 7;    
        uint32_t crc : 8;        
    } tx_fields;
    
    struct {
        uint32_t data : 16;       
        uint32_t rw_echo : 1;     
        uint32_t status : 5;      
        uint32_t reply_mode : 2;  
        uint32_t crc : 8;         
    } rx_fields;
    
    [[nodiscard]] static constexpr SPIFrame make_read(uint16_t addr) noexcept {
        SPIFrame frame{};
        frame.tx_fields.rw = 0;           // Read
        frame.tx_fields.address = (addr >> 3) & 0x7F;  // Upper 7 bits
        frame.tx_fields.data = addr & 0x07;            // Lower 3 bits in data
        frame.tx_fields.crc = 0;          // CRC calculated separately
        return frame;
    }
    
    [[nodiscard]] static constexpr SPIFrame make_write(uint16_t addr, uint16_t data) noexcept {
        SPIFrame frame{};
        frame.tx_fields.rw = 1;           // Write
        frame.tx_fields.address = (addr >> 3) & 0x7F;  // Upper 7 bits
        frame.tx_fields.data = data;
        frame.tx_fields.crc = 0;          // CRC calculated separately
        return frame;
    }
};
 
static_assert(sizeof(SPIFrame) == 4, "SPIFrame must be exactly 4 bytes");
 
enum class ReplyMode : uint8_t {
    REPLY_16BIT = 0b00,      
    REPLY_22BIT = 0b01,      
    CRITICAL_FAULT = 0b10,   
    RESERVED = 0b11          
};
 
enum class SPIStatus : uint8_t {
    NO_ERROR = 0b00000,          
    SPI_FRAME_ERROR = 0b00001,   
    CRC_ERROR = 0b00010,         
    WRITE_RO_REG = 0b00011,      
    INTERNAL_BUS_FAULT = 0b00100 
};
 
//==============================================================================
// REGISTER ADDRESSES - CENTRAL/GLOBAL REGISTERS
//==============================================================================
 
namespace CentralReg {
    constexpr uint16_t CH_CTRL        = 0x0000;  
    constexpr uint16_t GLOBAL_CONFIG  = 0x0002;  
    constexpr uint16_t GLOBAL_DIAG0   = 0x0003;  
    constexpr uint16_t GLOBAL_DIAG1   = 0x0004;  
    constexpr uint16_t GLOBAL_DIAG2   = 0x0005;  
    constexpr uint16_t VBAT_TH        = 0x0006;  
    constexpr uint16_t FB_FRZ         = 0x0007;  
    constexpr uint16_t FB_UPD         = 0x0008;  
    constexpr uint16_t WD_RELOAD      = 0x0009;  
    
    // Channel Group Diagnosis (0x000A + channel_group)
    constexpr uint16_t DIAG_ERR_CHGR0  = 0x000A;  
    constexpr uint16_t DIAG_ERR_CHGR1  = 0x000B;  
    constexpr uint16_t DIAG_ERR_CHGR2  = 0x000C;  
    constexpr uint16_t DIAG_ERR_CHGR3  = 0x000D;  
    constexpr uint16_t DIAG_ERR_CHGR4  = 0x000E;  
    constexpr uint16_t DIAG_ERR_CHGR5  = 0x000F;  
    
    constexpr uint16_t DIAG_WARN_CHGR0 = 0x0010;  
    constexpr uint16_t DIAG_WARN_CHGR1 = 0x0011;  
    constexpr uint16_t DIAG_WARN_CHGR2 = 0x0012;  
    constexpr uint16_t DIAG_WARN_CHGR3 = 0x0013;  
    constexpr uint16_t DIAG_WARN_CHGR4 = 0x0014;  
    constexpr uint16_t DIAG_WARN_CHGR5 = 0x0015;  
    
    constexpr uint16_t FAULT_MASK0    = 0x0016;  
    constexpr uint16_t FAULT_MASK1    = 0x0017;  
    constexpr uint16_t FAULT_MASK2    = 0x0018;  
    constexpr uint16_t CLK_DIV        = 0x0019;  
    constexpr uint16_t SFF_BIST       = 0x003F;  
    
    // Feedback/Status Registers
    constexpr uint16_t ICVID          = 0x0200;  
    constexpr uint16_t PIN_STAT       = 0x0201;  
    constexpr uint16_t FB_STAT        = 0x0202;  
    constexpr uint16_t FB_VOLTAGE1    = 0x0203;  
    constexpr uint16_t FB_VOLTAGE2    = 0x0204;  
    constexpr uint16_t CHIPID0        = 0x0205;  
    constexpr uint16_t CHIPID1        = 0x0206;  
    constexpr uint16_t CHIPID2        = 0x0207;  
}
 
//==============================================================================
// DEVICE IDENTIFICATION CONSTANTS
//==============================================================================
 
namespace DeviceID {
    constexpr uint16_t DEVICE_TYPE_MASK = 0xFF00;  
    constexpr uint16_t REVISION_MASK    = 0x00FF;  
    
    // Expected device type code for TLE92466ED (upper byte of ICVID)
    // Note: This should be confirmed from datasheet or actual device
    constexpr uint8_t EXPECTED_TYPE_92466ED = 0x92;  
    
    // Minimum supported silicon revision
    constexpr uint8_t MIN_REVISION = 0x00;  
    
    [[nodiscard]] constexpr bool is_valid_device(uint16_t icvid) noexcept {
        [[maybe_unused]] uint8_t device_type = (icvid >> 8) & 0xFF;
        // Accept device if communication is working (non-zero response)
        // Strict type checking can be enabled if exact ID is known
        return icvid != 0x0000 && icvid != 0xFFFF;
    }
    
    [[nodiscard]] constexpr uint8_t get_device_type(uint16_t icvid) noexcept {
        return (icvid >> 8) & 0xFF;
    }
    
    [[nodiscard]] constexpr uint8_t get_revision(uint16_t icvid) noexcept {
        return icvid & 0xFF;
    }
}
 
//==============================================================================
// CHANNEL REGISTER OFFSETS
//==============================================================================
 
namespace ChannelBase {
    constexpr uint16_t CH0 = 0x0100;  
    constexpr uint16_t CH1 = 0x0120;  
    constexpr uint16_t CH2 = 0x0140;  
    constexpr uint16_t CH3 = 0x0160;  
    constexpr uint16_t CH4 = 0x0180;  
    constexpr uint16_t CH5 = 0x01A0;  
    
    constexpr uint16_t SPACING = 0x0020;  
}
 
namespace ChannelReg {
    constexpr uint16_t SETPOINT         = 0x0000;  
    constexpr uint16_t CTRL             = 0x0001;  
    constexpr uint16_t PERIOD           = 0x0002;  
    constexpr uint16_t INTEGRATOR_LIMIT = 0x0003;  
    constexpr uint16_t DITHER_CLK_DIV   = 0x0004;  
    constexpr uint16_t DITHER_STEP      = 0x0005;  
    constexpr uint16_t DITHER_CTRL      = 0x0006;  
    constexpr uint16_t CH_CONFIG        = 0x0007;  
    constexpr uint16_t MODE             = 0x000C;  
    constexpr uint16_t TON              = 0x000D;  
    constexpr uint16_t CTRL_INT_THRESH  = 0x000E;  
    constexpr uint16_t FB_DC            = 0x0200;  
    constexpr uint16_t FB_VBAT          = 0x0201;  
    constexpr uint16_t FB_I_AVG         = 0x0202;  
    constexpr uint16_t FB_IMIN_IMAX     = 0x0203;  
    constexpr uint16_t FB_INT_THRESH    = 0x0205;  
}
 
//==============================================================================
// CH_CTRL REGISTER (0x0000) - Channel Control
//==============================================================================
 
namespace CH_CTRL {
    constexpr uint16_t EN_CH0       = (1 << 0);   
    constexpr uint16_t EN_CH1       = (1 << 1);   
    constexpr uint16_t EN_CH2       = (1 << 2);   
    constexpr uint16_t EN_CH3       = (1 << 3);   
    constexpr uint16_t EN_CH4       = (1 << 4);   
    constexpr uint16_t EN_CH5       = (1 << 5);   
    constexpr uint16_t CH_PAR_4_5   = (1 << 12);  
    constexpr uint16_t CH_PAR_0_3   = (1 << 13);  
    constexpr uint16_t CH_PAR_1_2   = (1 << 14);  
    constexpr uint16_t OP_MODE      = (1 << 15);  
    
    constexpr uint16_t ALL_CH_MASK  = 0x003F;     
    constexpr uint16_t ALL_PAR_MASK = 0x7000;     
    
    constexpr uint16_t DEFAULT      = 0x0000;     
    
    constexpr uint16_t CONFIG_MODE  = 0x0000;
    constexpr uint16_t MISSION_MODE = OP_MODE;
    
    [[nodiscard]] constexpr uint16_t channel_mask(uint8_t channel) noexcept {
        return (channel < 6) ? static_cast<uint16_t>(1 << channel) : 0;
    }
}
 
//==============================================================================
// GLOBAL_CONFIG REGISTER (0x0002) - Global Configuration
//==============================================================================
 
namespace GLOBAL_CONFIG {
    constexpr uint16_t CLK_WD_EN     = (1 << 0);   
    constexpr uint16_t SPI_WD_EN     = (1 << 1);   
    constexpr uint16_t CRC_EN        = (1 << 2);   
    constexpr uint16_t V1V5_UV_TEST  = (1 << 4);   
    constexpr uint16_t V1V5_OV_TEST  = (1 << 5);   
    constexpr uint16_t OT_TEST       = (1 << 12);  
    constexpr uint16_t UV_OV_SWAP    = (1 << 13);  
    constexpr uint16_t VIO_SEL       = (1 << 14);  
    
    constexpr uint16_t DEFAULT       = 0x4005;     
}
 
//==============================================================================
// GLOBAL_DIAG0 REGISTER (0x0003) - Global Diagnosis Register 0
//==============================================================================
 
namespace GLOBAL_DIAG0 {
    constexpr uint16_t VBAT_UV     = (1 << 0);   
    constexpr uint16_t VBAT_OV     = (1 << 1);   
    constexpr uint16_t VIO_UV      = (1 << 2);   
    constexpr uint16_t VIO_OV      = (1 << 3);   
    constexpr uint16_t VDD_UV      = (1 << 4);   
    constexpr uint16_t VDD_OV      = (1 << 5);   
    constexpr uint16_t CLK_NOK     = (1 << 6);   
    constexpr uint16_t COTERR      = (1 << 7);   
    constexpr uint16_t COTWARN     = (1 << 8);   
    constexpr uint16_t RES_EVENT   = (1 << 9);   
    constexpr uint16_t POR_EVENT   = (1 << 10);  
    constexpr uint16_t SPI_WD_ERR  = (1 << 14);  
    
    constexpr uint16_t DEFAULT     = 0x0600;     
    constexpr uint16_t FAULT_MASK  = 0x47FF;     
}
 
//==============================================================================
// GLOBAL_DIAG1 REGISTER (0x0004) - Global Diagnosis Register 1
//==============================================================================
 
namespace GLOBAL_DIAG1 {
    constexpr uint16_t VR_IREF_UV  = (1 << 0);   
    constexpr uint16_t VR_IREF_OV  = (1 << 1);   
    constexpr uint16_t VDD2V5_UV   = (1 << 2);   
    constexpr uint16_t VDD2V5_OV   = (1 << 3);   
    constexpr uint16_t REF_UV      = (1 << 4);   
    constexpr uint16_t REF_OV      = (1 << 5);   
    constexpr uint16_t VPRE_OV     = (1 << 6);   
    constexpr uint16_t HVADC_ERR   = (1 << 15);  
    
    constexpr uint16_t DEFAULT     = 0x0000;     
}
 
//==============================================================================
// GLOBAL_DIAG2 REGISTER (0x0005) - Global Diagnosis Register 2
//==============================================================================
 
namespace GLOBAL_DIAG2 {
    constexpr uint16_t REG_ECC_ERR = (1 << 1);   
    constexpr uint16_t OTP_ECC_ERR = (1 << 3);   
    constexpr uint16_t OTP_VIRGIN  = (1 << 4);   
    
    constexpr uint16_t DEFAULT     = 0x0000;     
}
 
//==============================================================================
// FB_STAT REGISTER (0x0202) - Feedback Status
//==============================================================================
 
namespace FB_STAT {
    constexpr uint16_t SUP_NOK_INT  = (1 << 0);  
    constexpr uint16_t SUP_NOK_EXT  = (1 << 1);  
    constexpr uint16_t EN_PROT      = (1 << 2);  
    constexpr uint16_t INIT_DONE    = (1 << 3);  
    constexpr uint16_t CLK_NOK_STAT = (1 << 6);  
}
 
//==============================================================================
// CHANNEL SETPOINT REGISTER - Per Channel
//==============================================================================
 
namespace SETPOINT {
    constexpr uint16_t TARGET_MASK      = 0x7FFF;  
    constexpr uint16_t AUTO_LIMIT_DIS   = (1 << 15); 
    
    constexpr uint16_t DEFAULT          = 0x0000;  
    
    constexpr uint16_t MAX_TARGET       = 0x6000;
    
    [[nodiscard]] constexpr uint16_t calculate_target(uint16_t current_ma, bool parallel_mode = false) noexcept {
        uint32_t max_current = parallel_mode ? 4000 : 2000;
        uint32_t target = (static_cast<uint32_t>(current_ma) * 32767UL) / max_current;
        // Saturate at MAX_TARGET
        if (target > MAX_TARGET) target = MAX_TARGET;
        return static_cast<uint16_t>(target);
    }
    
    [[nodiscard]] constexpr uint16_t calculate_current(uint16_t target, bool parallel_mode = false) noexcept {
        uint32_t max_current = parallel_mode ? 4000 : 2000;
        uint32_t current = (static_cast<uint32_t>(target & TARGET_MASK) * max_current) / 32767UL;
        return static_cast<uint16_t>(current);
    }
}
 
//==============================================================================
// CHANNEL CTRL REGISTER - Per Channel
//==============================================================================
 
namespace CH_CTRL_REG {
    constexpr uint16_t MIN_INT_THRESH_MASK   = 0x00FF;  
    constexpr uint16_t PWM_PERIOD_CALC_MODE  = (1 << 8);   
    constexpr uint16_t OLSG_WARN_WINDOW_MASK = 0x3E00;  
    constexpr uint16_t OLSG_WARN_WINDOW_SHIFT = 9;      
    constexpr uint16_t OLSG_WARN_EN          = (1 << 14); 
    
    constexpr uint16_t DEFAULT = 0x4600;  
}
 
//==============================================================================
// CH_CONFIG REGISTER - Per Channel Configuration
//==============================================================================
 
namespace CH_CONFIG {
    // Slew rate control [1:0]
    constexpr uint16_t SLEWR_1V0_US   = 0b00;     
    constexpr uint16_t SLEWR_2V5_US   = 0b01;     
    constexpr uint16_t SLEWR_5V0_US   = 0b10;     
    constexpr uint16_t SLEWR_10V0_US  = 0b11;     
    constexpr uint16_t SLEWR_MASK     = 0x0003;   
    
    // OFF-state diagnostic current [3:2]
    constexpr uint16_t I_DIAG_80UA    = (0 << 2); 
    constexpr uint16_t I_DIAG_190UA   = (1 << 2); 
    constexpr uint16_t I_DIAG_720UA   = (2 << 2); 
    constexpr uint16_t I_DIAG_1250UA  = (3 << 2); 
    constexpr uint16_t I_DIAG_MASK    = 0x000C;   
    
    // Open load threshold relative to setpoint [6:4]
    constexpr uint16_t OL_TH_DISABLED = (0 << 4); 
    constexpr uint16_t OL_TH_1_8      = (1 << 4); 
    constexpr uint16_t OL_TH_2_8      = (2 << 4); 
    constexpr uint16_t OL_TH_3_8      = (3 << 4); 
    constexpr uint16_t OL_TH_4_8      = (4 << 4); 
    constexpr uint16_t OL_TH_5_8      = (5 << 4); 
    constexpr uint16_t OL_TH_6_8      = (6 << 4); 
    constexpr uint16_t OL_TH_7_8      = (7 << 4); 
    constexpr uint16_t OL_TH_MASK     = 0x0070;   
    
    // Fixed open load threshold [12:7]
    constexpr uint16_t OL_TH_FIXED_SHIFT = 7;
    constexpr uint16_t OL_TH_FIXED_MASK  = 0x1F80;
    
    constexpr uint16_t OC_DIAG_EN     = (1 << 13); 
    
    // OFF-state diagnostic control [15:14]
    constexpr uint16_t OFF_DIAG_ENABLED    = (0 << 14); 
    constexpr uint16_t OFF_DIAG_LS_ONLY    = (1 << 14); 
    constexpr uint16_t OFF_DIAG_HS_ONLY    = (2 << 14); 
    constexpr uint16_t OFF_DIAG_MASK       = 0xC000;    
    
    constexpr uint16_t DEFAULT = 0x0003;  
}
 
//==============================================================================
// MODE REGISTER - Channel Mode
//==============================================================================
 
namespace CH_MODE {
    constexpr uint16_t OFF              = 0x0000;  
    constexpr uint16_t ICC_CURRENT_CTRL = 0x0001;  
    constexpr uint16_t DIRECT_DRIVE_SPI = 0x0002;  
    constexpr uint16_t DIRECT_DRIVE_DRV0= 0x0003;  
    constexpr uint16_t DIRECT_DRIVE_DRV1= 0x0004;  
    constexpr uint16_t FREE_RUN_MEAS    = 0x000C;  
    constexpr uint16_t MODE_MASK        = 0x000F;  
    
    constexpr uint16_t DEFAULT = OFF;  
}
 
//==============================================================================
// DITHER CONTROL REGISTER - Per Channel
//==============================================================================
 
namespace DITHER_CTRL {
    constexpr uint16_t STEP_SIZE_MASK    = 0x0FFF;  
    constexpr uint16_t DEEP_DITHER       = (1 << 13); 
    constexpr uint16_t FAST_MEAS_DITH    = (0 << 14); 
    constexpr uint16_t FAST_MEAS_HALF    = (1 << 14); 
    constexpr uint16_t FAST_MEAS_QUAD    = (2 << 14); 
    constexpr uint16_t FAST_MEAS_MASK    = 0xC000;    
    
    constexpr uint16_t DEFAULT = 0x0000;  
}
 
//==============================================================================
// DITHER STEP REGISTER - Per Channel
//==============================================================================
 
namespace DITHER_STEP {
    constexpr uint16_t FLAT_MASK  = 0x00FF;  
    constexpr uint16_t STEPS_SHIFT = 8;      
    constexpr uint16_t STEPS_MASK = 0xFF00;  
    
    constexpr uint16_t DEFAULT = 0x0000;     
}
 
//==============================================================================
// HELPER ENUMERATIONS
//==============================================================================
 
enum class Channel : uint8_t {
    CH0 = 0,  
    CH1 = 1,  
    CH2 = 2,  
    CH3 = 3,  
    CH4 = 4,  
    CH5 = 5,  
    
    COUNT = 6 
};
 
enum class ChannelMode : uint8_t {
    OFF = 0x0,             
    ICC = 0x1,             
    DIRECT_DRIVE_SPI = 0x2,
    DIRECT_DRIVE_DRV0 = 0x3,
    DIRECT_DRIVE_DRV1 = 0x4,
    FREE_RUN_MEAS = 0xC    
};
 
enum class SlewRate : uint8_t {
    SLOW_1V0_US = 0,    
    MEDIUM_2V5_US = 1,  
    FAST_5V0_US = 2,    
    FASTEST_10V0_US = 3 
};
 
enum class DiagCurrent : uint8_t {
    I_80UA = 0,    
    I_190UA = 1,   
    I_720UA = 2,   
    I_1250UA = 3   
};
 
enum class ParallelPair : uint8_t {
    NONE = 0,      
    CH0_CH3 = 1,   
    CH1_CH2 = 2,   
    CH4_CH5 = 3    
};
 
//==============================================================================
// ADDRESS CALCULATION HELPERS
//==============================================================================
 
[[nodiscard]] constexpr uint16_t get_channel_base(Channel channel) noexcept {
    return ChannelBase::CH0 + (static_cast<uint16_t>(channel) * ChannelBase::SPACING);
}
 
[[nodiscard]] constexpr uint16_t get_channel_register(Channel channel, uint16_t offset) noexcept {
    return get_channel_base(channel) + offset;
}
 
[[nodiscard]] constexpr uint8_t to_index(Channel ch) noexcept {
    return static_cast<uint8_t>(ch);
}
 
[[nodiscard]] constexpr bool is_valid_channel(Channel ch) noexcept {
    return to_index(ch) < static_cast<uint8_t>(Channel::COUNT);
}
 
//==============================================================================
// CRC CALCULATION (SAE J1850)
//==============================================================================
 
[[nodiscard]] constexpr uint8_t calculate_crc8_j1850(const uint8_t* data, size_t length) noexcept {
    constexpr uint8_t POLY = 0x1D;
    uint8_t crc = 0xFF;
    
    for (size_t i = 0; i < length; ++i) {
        crc ^= data[i];
        for (uint8_t bit = 0; bit < 8; ++bit) {
            if (crc & 0x80) {
                crc = (crc << 1) ^ POLY;
            } else {
                crc = (crc << 1);
            }
        }
    }
    
    return crc ^ 0xFF;
}
 
[[nodiscard]] inline uint8_t calculate_frame_crc(const SPIFrame& frame) noexcept {
    const uint8_t* bytes = reinterpret_cast<const uint8_t*>(&frame);
    // Calculate CRC on bytes 0-2 (excluding CRC byte itself at position 3)
    return calculate_crc8_j1850(bytes, 3);
}
 
[[nodiscard]] inline bool verify_frame_crc(const SPIFrame& frame) noexcept {
    SPIFrame temp = frame;
    uint8_t received_crc = temp.tx_fields.crc;
    temp.tx_fields.crc = 0;
    uint8_t calculated_crc = calculate_frame_crc(temp);
    return (received_crc == calculated_crc);
}
 
} // namespace TLE92466ED
 
#endif // TLE92466ED_REGISTERS_HPP