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1.10.0
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HF-TMC9660 Driver 0.1.0-dev
Hardware Agnostic C++ Driver for the TMC9660
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Bootloader configuration register addresses. More...
Variables | |
| constexpr uint32_t | BASE = 0x00020000 |
| Base offset of the configuration registers inside bank 5. | |
| constexpr uint32_t | LDO_CONFIG = BASE + 0x00 |
| LDO configuration register address. | |
| constexpr uint32_t | UART_ADDR = BASE + 0x02 |
| UART device/host address register. | |
| constexpr uint32_t | RS485_DELAY = BASE + 0x04 |
| RS485 TXEN delay configuration register. | |
| constexpr uint32_t | COMM_CONFIG = BASE + 0x06 |
| Communication interface selection register. | |
| constexpr uint32_t | BOOT_CONFIG = BASE + 0x08 |
| Boot configuration register. | |
| constexpr uint32_t | SPI_FLASH = BASE + 0x0A |
| SPI flash configuration register. | |
| constexpr uint32_t | I2C_CONFIG = BASE + 0x0C |
| I2C EEPROM configuration register. | |
| constexpr uint32_t | GPIO_OUT = BASE + 0x0E |
| GPIO output level register. | |
| constexpr uint32_t | GPIO_DIR = BASE + 0x10 |
| GPIO direction register. | |
| constexpr uint32_t | GPIO_PU = BASE + 0x12 |
| GPIO pull-up enable register. | |
| constexpr uint32_t | GPIO_PD = BASE + 0x14 |
| GPIO pull-down enable register. | |
| constexpr uint32_t | GPIO_EXT = BASE + 0x16 |
| GPIO extended configuration register. | |
| constexpr uint32_t | CLOCK_CONFIG = BASE + 0x18 |
| Clock configuration register. | |
| constexpr uint32_t | HALL_CONFIG = BASE + 0x20 |
| Hall encoder configuration register. | |
| constexpr uint32_t | ABN1_CONFIG = BASE + 0x20 |
| ABN encoder 1 configuration register. | |
| constexpr uint32_t | ABN2_CONFIG = BASE + 0x22 |
| ABN encoder 2 configuration register. | |
| constexpr uint32_t | REF_CONFIG = BASE + 0x22 |
| Reference switches configuration register. | |
| constexpr uint32_t | STEPDIR_CONFIG = BASE + 0x22 |
| Step/Direction interface configuration register. | |
| constexpr uint32_t | SPI_ENC_CONFIG = BASE + 0x26 |
| SPI encoder configuration register. | |
| constexpr uint32_t | MECH_BRAKE_CONFIG = BASE + 0x24 |
| Mechanical brake configuration register. | |
| constexpr uint32_t | BRAKECHOPPER_CONFIG = BASE + 0x24 |
| Brake chopper configuration register. | |
| constexpr uint32_t | MEM_STORAGE_CONFIG = BASE + 0x28 |
| External memory storage selection register. | |
Bootloader configuration register addresses.
This namespace contains the memory addresses for all bootloader configuration registers within bank 5 (CONFIG memory bank). These addresses are used to configure the TMC9660's bootloader behavior and hardware settings.
ABN encoder 1 configuration register.
Configures ABN encoder 1 pins and enable settings for incremental encoder feedback. This register is shared with Hall encoder configuration at offset 0x20.
ABN encoder 2 configuration register.
Configures ABN encoder 2 pins and enable settings for second incremental encoder. This register is shared with reference switches and step/direction at offset 0x22.
Base offset of the configuration registers inside bank 5.
All bootloader configuration registers are located in memory bank 5, starting at this base address.
Boot configuration register.
Controls the bootloader behavior including boot mode selection, motor control startup, and fault handling options.
Brake chopper configuration register.
Configures brake chopper output pin and enable settings for dynamic braking. This register is shared with mechanical brake at offset 0x24.
Clock configuration register.
Configures the system clock source, PLL settings, and frequency dividers for optimal performance.
Communication interface selection register.
Configures which communication interfaces are enabled (UART/SPI/RS485) and their associated pin assignments and parameters.
GPIO direction register.
Configures GPIO pins 0-15 as inputs or outputs during bootloader operation.
GPIO extended configuration register.
Configures GPIO pins 16-18 and analog GPIOs 2-5, including output levels, directions, and pull settings.
GPIO output level register.
Sets the initial output levels for GPIO pins 0-15 during bootloader operation.
GPIO pull-down enable register.
Enables internal pull-down resistors for GPIO pins 0-15 during bootloader operation.
GPIO pull-up enable register.
Enables internal pull-up resistors for GPIO pins 0-15 during bootloader operation.
Hall encoder configuration register.
Configures Hall sensor pins and enable settings for BLDC motor feedback. This register is shared with ABN1 configuration at offset 0x20.
I2C EEPROM configuration register.
Configures external I2C EEPROM interface including pin assignments, address bits, and communication frequency.
LDO configuration register address.
Configures the on-chip LDO regulators for VEXT1 and VEXT2 outputs, including voltage levels, slope control, and fault detection.
Mechanical brake configuration register.
Configures mechanical brake output pin and enable settings. This register is shared with brake chopper at offset 0x24.
External memory storage selection register.
Configures which external memory types are used for storing TMCL scripts and parameter data.
Reference switches configuration register.
Configures reference switch pins for limit detection and homing. This register is shared with ABN2 and step/direction at offset 0x22.
RS485 TXEN delay configuration register.
Configures the timing delays for RS485 transmit enable signal to ensure proper half-duplex communication.
SPI encoder configuration register.
Configures SPI encoder interface including block selection, communication mode, frequency, and chip select settings.
SPI flash configuration register.
Configures external SPI flash memory interface including chip select pin, frequency divider, and enable settings.
Step/Direction interface configuration register.
Configures step and direction pins for stepper motor control. This register is shared with ABN2 and reference switches at offset 0x22.
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