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HF-TMC9660 Driver 0.1.0-dev
Hardware Agnostic C++ Driver for the TMC9660
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Bootloader configuration namespace containing all configuration structures and enums. More...
Enumerations | |
| enum class | LDOVoltage : uint8_t { Disabled = 0 , V2_5 = 1 , V3_3 = 2 , V5_0 = 3 } |
| Enumerations describing bootloader configuration options. More... | |
| enum class | LDOSlope : uint8_t { Slope3ms = 0 , Slope1_5ms = 1 , Slope0_75ms = 2 , Slope0_37ms = 3 } |
| LDO output slope control for power-up characteristics. More... | |
| enum class | BootMode : uint8_t { Register = 1 , Parameter = 2 } |
| Boot mode selection for motor control system startup. More... | |
| enum class | UartRxPin : uint8_t { GPIO7 = 0 , GPIO1 = 1 } |
| UART receive pin selection for bootloader communication. More... | |
| enum class | UartTxPin : uint8_t { GPIO6 = 0 , GPIO0 = 1 } |
| UART transmit pin selection for bootloader communication. More... | |
| enum class | BaudRate : uint8_t { BR9600 = 0 , BR19200 , BR38400 , BR57600 , BR115200 , BR1000000 , Auto8x , Auto16x } |
| UART baud rate configuration for bootloader communication. More... | |
| enum class | RS485TxEnPin : uint8_t { None = 0 , GPIO8 = 1 , GPIO2 = 2 } |
| RS485 transmit enable pin selection for half-duplex communication. More... | |
| enum class | SPIInterface : uint8_t { SPI0 = 0 , SPI1 = 1 } |
| SPI interface selection for bootloader and flash communication. More... | |
| enum class | SPI0SckPin : uint8_t { GPIO6 = 0 , GPIO11 = 1 } |
| SPI0 clock pin selection for bootloader communication. More... | |
| enum class | SPIFlashFreq : uint8_t { Div1 = 0 , Div2 = 1 , Div4 = 3 } |
| SPI flash frequency divider configuration. More... | |
| enum class | I2CSdaPin : uint8_t { GPIO5 = 0 , GPIO11 = 1 , GPIO14 = 2 } |
| I2C data pin selection for external EEPROM communication. More... | |
| enum class | I2CSclPin : uint8_t { GPIO4 = 0 , GPIO12 = 1 , GPIO13 = 2 } |
| I2C clock pin selection for external EEPROM communication. More... | |
| enum class | I2CFreq : uint8_t { Freq100k = 0 , Freq200k , Freq400k , Freq800k } |
| I2C communication frequency configuration. More... | |
| enum class | ClockSource : uint8_t { Internal = 0 , External = 1 } |
| System clock source selection. More... | |
| enum class | ExtSourceType : uint8_t { Oscillator = 0 , Clock = 1 } |
| External clock source type configuration. More... | |
| enum class | XtalDrive : uint8_t { Freq8MHz = 1 , Freq16MHz = 3 , Freq24MHz = 5 , Freq32MHz = 6 } |
| Crystal drive strength configuration for external oscillators. More... | |
| enum class | SysClkSource : uint8_t { IntOsc = 0 , PLL = 1 } |
| System clock source selection after initial oscillator. More... | |
| enum class | SysClkDiv : uint8_t { Div1 = 0 , Div15MHz = 3 } |
| System clock divider configuration. More... | |
| enum class | HallUPin : uint8_t { GPIO2 = 0 , GPIO7 = 1 , GPIO9 = 2 } |
| Hall encoder U-phase pin selection for BLDC motor feedback. More... | |
| enum class | HallVPin : uint8_t { GPIO3 = 0 , GPIO15 = 1 } |
| Hall encoder V-phase pin selection for BLDC motor feedback. More... | |
| enum class | HallWPin : uint8_t { GPIO4 = 0 , GPIO8 = 1 , GPIO10 = 2 } |
| Hall encoder W-phase pin selection for BLDC motor feedback. More... | |
| enum class | ABN1APin : uint8_t { GPIO5 = 0 , GPIO8 = 1 , GPIO17 = 2 } |
| ABN encoder 1 A-phase pin selection for incremental encoder feedback. More... | |
| enum class | ABN1BPin : uint8_t { GPIO1 = 0 , GPIO13 = 1 , GPIO18 = 2 } |
| ABN encoder 1 B-phase pin selection for incremental encoder feedback. More... | |
| enum class | ABN1NPin : uint8_t { Disabled = 0 , GPIO14 = 1 , GPIO16 = 2 } |
| ABN encoder 1 index pin selection for incremental encoder feedback. More... | |
| enum class | ABN2APin : uint8_t { GPIO6 = 0 , GPIO15 = 1 } |
| ABN encoder 2 A-phase pin selection for second incremental encoder. More... | |
| enum class | ABN2BPin : uint8_t { GPIO7 = 0 , GPIO11 = 1 , GPIO16 = 2 } |
| ABN encoder 2 B-phase pin selection for second incremental encoder. More... | |
| enum class | RefLPin : uint8_t { Disabled = 0 , GPIO2 = 1 , GPIO12 = 2 , GPIO16 = 3 } |
| Reference switch left pin selection for limit switch detection. More... | |
| enum class | RefRPin : uint8_t { Disabled = 0 , GPIO3 = 1 , GPIO18 = 2 } |
| Reference switch right pin selection for limit switch detection. More... | |
| enum class | RefHPin : uint8_t { Disabled = 0 , GPIO4 = 1 , GPIO7 = 2 , GPIO15 = 3 , GPIO17 = 4 } |
| Reference switch home pin selection for home position detection. More... | |
| enum class | StepPin : uint8_t { GPIO7 = 0 , GPIO11 = 1 , GPIO16 = 2 } |
| Step pin selection for step/direction interface. More... | |
| enum class | DirPin : uint8_t { GPIO6 = 0 , GPIO15 = 1 } |
| Direction pin selection for step/direction interface. More... | |
| enum class | SPIEncBlock : uint8_t { SPI0 = 0 , SPI1 = 1 } |
| SPI encoder interface block selection. More... | |
| enum class | SPIEncMode : uint8_t { Mode0 = 0 , Mode1 = 1 , Mode2 = 2 , Mode3 = 3 } |
| SPI encoder communication mode configuration. More... | |
| enum class | SPIEncFreq : uint8_t { Div4 = 0 , Div5 = 1 , Div6 = 2 , Div7 = 3 , Div8 = 4 , Div9 = 5 , Div10 = 6 , Div11 = 7 , Div12 = 8 , Div13 = 9 , Div14 = 10 , Div15 = 11 , Div16 = 12 , Div17 = 13 , Div18 = 14 , Div19 = 15 } |
| SPI encoder clock frequency divider configuration. More... | |
| enum class | SPIEncCSPin : uint8_t { GPIO8 = 0 , GPIO12 = 1 , GPIO13 = 2 , GPIO16 = 3 , GPIO15_SPI1 = 0 } |
| SPI encoder chip select pin selection. More... | |
| enum class | SPIEncCSPol : uint8_t { ActiveHigh = 0 , ActiveLow = 1 } |
| SPI encoder chip select polarity configuration. More... | |
| enum class | MechBrakeOutput : uint8_t { GPIO8 = 0 , GPIO10 = 1 , GPIO18 = 2 , Y2_LS = 3 } |
| Mechanical brake output pin selection. More... | |
| enum class | BrakeChopperOutput : uint8_t { GPIO0 = 0 , GPIO1 = 1 , GPIO2 = 2 , GPIO3 = 3 , GPIO4 = 4 , GPIO5 = 5 , GPIO6 = 6 , GPIO7 = 7 , GPIO8 = 8 , GPIO9 = 9 , GPIO10 = 10 , GPIO11 = 11 , GPIO12 = 12 , GPIO13 = 13 , GPIO14 = 14 , GPIO15 = 15 , GPIO16 = 16 , GPIO17 = 17 , GPIO18 = 18 , Y2_HS = 19 } |
| Brake chopper output pin selection for dynamic braking. More... | |
| enum class | MemStorage : uint8_t { Disabled = 0 , SPIFlash = 1 , I2CEEPROM = 2 } |
| External memory storage type selection. More... | |
Bootloader configuration namespace containing all configuration structures and enums.
This namespace contains all the configuration structures, enumerations, and constants needed to configure the TMC9660 bootloader. These structures define hardware pin assignments, communication parameters, power supply settings, and system behavior options.
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ABN encoder 1 A-phase pin selection for incremental encoder feedback.
Selects which GPIO pin is used for the ABN encoder 1 A-phase signal. Used for precise position and velocity feedback from incremental encoders.
| Enumerator | |
|---|---|
| GPIO5 | Use GPIO5 for ABN1 A-phase (default) |
| GPIO8 | Use GPIO8 for ABN1 A-phase. |
| GPIO17 | Use GPIO17 for ABN1 A-phase. |
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ABN encoder 1 B-phase pin selection for incremental encoder feedback.
Selects which GPIO pin is used for the ABN encoder 1 B-phase signal. Used for precise position and velocity feedback from incremental encoders.
| Enumerator | |
|---|---|
| GPIO1 | Use GPIO1 for ABN1 B-phase (default) |
| GPIO13 | Use GPIO13 for ABN1 B-phase. |
| GPIO18 | Use GPIO18 for ABN1 B-phase. |
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ABN encoder 1 index pin selection for incremental encoder feedback.
Selects which GPIO pin is used for the ABN encoder 1 index (Z) signal. The index signal provides a reference position for absolute positioning.
| Enumerator | |
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| Disabled | No index pin (index signal not used) |
| GPIO14 | Use GPIO14 for ABN1 index signal. |
| GPIO16 | Use GPIO16 for ABN1 index signal. |
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ABN encoder 2 B-phase pin selection for second incremental encoder.
Selects which GPIO pin is used for the ABN encoder 2 B-phase signal. Used for dual-encoder applications or secondary position feedback.
| Enumerator | |
|---|---|
| GPIO7 | Use GPIO7 for ABN2 B-phase (default) |
| GPIO11 | Use GPIO11 for ABN2 B-phase. |
| GPIO16 | Use GPIO16 for ABN2 B-phase. |
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UART baud rate configuration for bootloader communication.
Configures the UART communication speed. Auto modes detect the baud rate automatically by analyzing the received data pattern.
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Boot mode selection for motor control system startup.
Determines which motor control mode the TMC9660 will enter after bootloader configuration is complete and START_MOTOR_CTRL is set.
| Enumerator | |
|---|---|
| Register | Register mode - direct register access for motor control. |
| Parameter | Parameter mode - TMCL command-based motor control (recommended) |
Brake chopper output pin selection for dynamic braking.
Selects which output is used for the brake chopper circuit. Used for dynamic braking to quickly stop the motor by shorting the windings.
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System clock source selection.
Determines whether the TMC9660 uses its internal oscillator or an external clock source for system timing.
| Enumerator | |
|---|---|
| Internal | Use internal oscillator (default, no external components needed) |
| External | Use external clock source (requires external crystal/oscillator) |
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Direction pin selection for step/direction interface.
Selects which GPIO pin is used for the direction signal in step/direction mode. Used for controlling stepper motors or providing direction signals to external controllers.
| Enumerator | |
|---|---|
| GPIO6 | Use GPIO6 for direction signal (default) |
| GPIO15 | Use GPIO15 for direction signal. |
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External clock source type configuration.
Specifies the type of external clock source when ClockSource::External is selected. This affects the input buffer configuration and clock processing.
| Enumerator | |
|---|---|
| Oscillator | External crystal oscillator (requires external crystal) |
| Clock | External clock signal (digital clock input) |
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Hall encoder U-phase pin selection for BLDC motor feedback.
Selects which GPIO pin is used for the Hall sensor U-phase signal. Used for BLDC motor commutation and position feedback.
| Enumerator | |
|---|---|
| GPIO2 | Use GPIO2 for Hall U-phase (default) |
| GPIO7 | Use GPIO7 for Hall U-phase. |
| GPIO9 | Use GPIO9 for Hall U-phase. |
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Hall encoder W-phase pin selection for BLDC motor feedback.
Selects which GPIO pin is used for the Hall sensor W-phase signal. Used for BLDC motor commutation and position feedback.
| Enumerator | |
|---|---|
| GPIO4 | Use GPIO4 for Hall W-phase (default) |
| GPIO8 | Use GPIO8 for Hall W-phase. |
| GPIO10 | Use GPIO10 for Hall W-phase. |
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I2C communication frequency configuration.
Sets the I2C clock frequency for external EEPROM communication. Higher frequencies enable faster data transfer but may be less reliable.
| Enumerator | |
|---|---|
| Freq100k | 100 kHz (standard mode, most compatible) |
| Freq200k | 200 kHz (fast mode) |
| Freq400k | 400 kHz (fast mode plus) |
| Freq800k | 800 kHz (high speed mode, fastest) |
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LDO output slope control for power-up characteristics.
Controls the rise time of the LDO output voltage during power-up. Slower slopes reduce inrush current but increase power-up time.
| Enumerator | |
|---|---|
| Slope3ms | 3ms rise time (slowest, lowest inrush current) |
| Slope1_5ms | 1.5ms rise time |
| Slope0_75ms | 0.75ms rise time |
| Slope0_37ms | 0.37ms rise time (fastest, highest inrush current) |
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Enumerations describing bootloader configuration options.
These enumerations define the various configuration options available for the TMC9660 bootloader, including voltage settings, communication parameters, and hardware pin configurations.
LDO voltage configuration options for external power supplies.
Configures the on-chip LDO regulators for VEXT1 and VEXT2 outputs. These voltages power external components connected to the TMC9660.
| Enumerator | |
|---|---|
| Disabled | LDO output disabled. |
| V2_5 | 2.5V output voltage |
| V3_3 | 3.3V output voltage |
| V5_0 | 5.0V output voltage |
Mechanical brake output pin selection.
Selects which output is used to control an external mechanical brake. Used for holding motor position when power is removed.
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Reference switch home pin selection for home position detection.
Selects which GPIO pin is used for the home reference switch signal. Used for detecting the home position during homing sequences.
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Reference switch left pin selection for limit switch detection.
Selects which GPIO pin is used for the left reference switch signal. Used for detecting mechanical limits and home position.
| Enumerator | |
|---|---|
| Disabled | No left reference switch (disabled) |
| GPIO2 | Use GPIO2 for left reference switch. |
| GPIO12 | Use GPIO12 for left reference switch. |
| GPIO16 | Use GPIO16 for left reference switch. |
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Reference switch right pin selection for limit switch detection.
Selects which GPIO pin is used for the right reference switch signal. Used for detecting mechanical limits and home position.
| Enumerator | |
|---|---|
| Disabled | No right reference switch (disabled) |
| GPIO3 | Use GPIO3 for right reference switch. |
| GPIO18 | Use GPIO18 for right reference switch. |
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RS485 transmit enable pin selection for half-duplex communication.
Selects which GPIO pin controls the RS485 transceiver's transmit enable. When None is selected, RS485 mode is disabled.
| Enumerator | |
|---|---|
| None | No RS485 TX enable pin (RS485 disabled) |
| GPIO8 | Use GPIO8 for RS485 TX enable. |
| GPIO2 | Use GPIO2 for RS485 TX enable. |
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SPI encoder chip select pin selection.
Selects which GPIO pin is used for the SPI encoder chip select signal. The available pins depend on which SPI interface is selected.
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SPI encoder chip select polarity configuration.
Configures the active level of the chip select signal for SPI encoder communication. Most SPI devices use active-low chip select.
| Enumerator | |
|---|---|
| ActiveHigh | Chip select active high (CS high = selected) |
| ActiveLow | Chip select active low (CS low = selected, most common) |
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SPI encoder clock frequency divider configuration.
Controls the SPI clock frequency for encoder communication. Higher divider values result in slower, more reliable communication.
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SPI encoder communication mode configuration.
Configures the SPI mode for encoder communication. Different encoders may require different SPI modes for proper communication.
| Enumerator | |
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| Mode0 | SPI Mode 0 (CPOL=0, CPHA=0) |
| Mode1 | SPI Mode 1 (CPOL=0, CPHA=1) |
| Mode2 | SPI Mode 2 (CPOL=1, CPHA=0) |
| Mode3 | SPI Mode 3 (CPOL=1, CPHA=1) |
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SPI flash frequency divider configuration.
Controls the SPI clock frequency for external flash communication. Higher divider values result in slower, more reliable communication.
| Enumerator | |
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| Div1 | No division (fastest, may be unreliable) |
| Div2 | Divide by 2 (medium speed) |
| Div4 | Divide by 4 (slowest, most reliable) |
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SPI interface selection for bootloader and flash communication.
The TMC9660 has two physical SPI interfaces: SPI0 and SPI1.
CRITICAL: BL_SPI_SELECT (bit 2 of COMM_CONFIG) has OPPOSITE meanings:
This enum uses the PHYSICAL interface names (SPI0/SPI1). The driver handles the bit inversion automatically in applyConfiguration().
Constraint: If both bootloader and flash are enabled, they MUST use different SPI interfaces (one on SPI0, the other on SPI1).
| Enumerator | |
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| SPI0 | Physical SPI0 interface. |
| SPI1 | Physical SPI1 interface. |
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Step pin selection for step/direction interface.
Selects which GPIO pin is used for the step signal in step/direction mode. Used for controlling stepper motors or providing step pulses to external controllers.
| Enumerator | |
|---|---|
| GPIO7 | Use GPIO7 for step signal (default) |
| GPIO11 | Use GPIO11 for step signal. |
| GPIO16 | Use GPIO16 for step signal. |
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System clock source selection after initial oscillator.
Determines whether the system clock is derived directly from the oscillator or through the PLL (Phase-Locked Loop) for frequency multiplication.
| Enumerator | |
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| IntOsc | Use internal oscillator directly (lower power, fixed frequency) |
| PLL | Use PLL for frequency multiplication (higher performance, configurable) |
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Crystal drive strength configuration for external oscillators.
Configures the drive strength of the internal oscillator when using an external crystal. Higher drive strength is needed for higher frequency crystals.