max22200.hpp File Reference

Main driver class for MAX22200 octal solenoid and motor driver. More...

#include "max22200_registers.hpp"
#include "max22200_types.hpp"
#include "max22200_spi_interface.hpp"
#include "max22200_version.h"
#include <cstdint>
#include "../src/max22200.ipp"

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Classes
class	max22200::MAX22200< SpiType >

Namespaces
namespace	max22200

Functions
const char *	max22200::GetDriverVersion () noexcept

Detailed Description

Main driver class for MAX22200 octal solenoid and motor driver.

This file provides the main MAX22200 driver class template that implements the two-phase SPI protocol per MAX22200 datasheet (Rev 1, 3/25, Document 19-100531).

Two-Phase SPI Protocol

The MAX22200 uses a two-phase SPI protocol for all register access:

Phase 1: Command Register Write

• CMD pin HIGH (must be held HIGH during entire transfer)
• Write 8-bit Command Register (1 byte SPI transfer)
• Device responds with STATUS[7:0] (Fault Flag Byte) on SDO
• Check for communication error: STATUS[7:0] = 0x04 (COMER flag)

Phase 2: Data Transfer

• CMD pin LOW (must be LOW for data transfer)
• Read or write data register:
  • 8-bit mode: Transfer 1 byte (MSB only, for fast updates)
  • 32-bit mode: Transfer 4 bytes (full register)

Initialization Sequence

Per datasheet Figure 6 (Programming Flow Chart):

1. Power-up: Set ENABLE pin HIGH, wait 0.5ms (tEN)
2. Read STATUS: Clear UVM flag and deassert nFAULT pin
3. Write STATUS: Set ACTIVE=1, configure HW (CMxy bits), set fault masks
4. Configure Channels: Write CFG_CHx for each channel (HIT/HOLD currents, timing, etc.)
5. Read STATUS: Verify UVM cleared and no faults
6. Ready: Channels can now be activated via ONCH bits

Timing Specifications

• Enable time (tEN): 0.5ms from ENABLE rising edge to SPI ready
• Wake-up time (tWU): 2.5ms from ACTIVE=1 to normal operation (OUT_ active)
• Disable time (tDIS): 2.5ms from ENABLE falling edge to OUT_ tristate
• Dead time (tDEAD): 200ns dead zone to prevent current feedthrough
• SPI clock period (tCLK): Minimum 100ns (max 10MHz standalone, 5MHz daisy-chain)

Restrictions and Limitations

• VDRnCDR and HSnLS bits can only be modified when:
  • All channels are OFF (ONCHx = 0 for all channels)
  • Both TRIGA and TRIGB inputs are logic-low
• CDR mode is only supported in low-side operation (HSnLS = 0)
• High-side mode (HSnLS = 1) only supports VDR mode
• Channel-pair mode (CMxy) can only be changed when both channels in the pair are OFF
• HFS, SRC, and DPM are only available for low-side applications

Fast 8-Bit Updates

For low-latency control, certain operations can use 8-bit MSB-only transfers:

• Channel ON/OFF: Write STATUS[31:24] (ONCH byte) — fast channel activation
• HOLD current update: Write CFG_CHx[31:24] (HOLD + HFS) — dynamic current control
• OCP status: Read FAULT[31:24] (OCP byte) — quick fault check

Note

All SPI transfers must use Mode 0 (CPOL=0, CPHA=0).

The CMD pin must be held HIGH during the rising edge of CSB for Command Register writes.

Communication errors (COMER) are detected by checking STATUS[7:0] = 0x04 after Command Register write.

Copyright

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