Chopper and driver configuration register (CHOPCONF) More...

#include <tmc51x0_registers.hpp>

Public Attributes
uint32_t	value

struct {

uint32_t toff: 4
	Bits 3..0: Off time and driver enable. More...

uint32_t hstrt_tfd: 3
	Bits 6..4: HSTRT (chm=0) or TFD[2..0] (chm=1) More...

uint32_t hend_offset: 4
	Bits 10..7: HEND (chm=0) or OFFSET (chm=1) More...

uint32_t tfd_3: 1
	Bit 11: TFD[3] (chm=1) or reserved (chm=0) More...

uint32_t disfdcc: 1
	Bit 12: Fast decay mode (chm=1) More...

uint32_t reserved1: 1
	Bit 13: Reserved, set to 0. More...

uint32_t chm: 1
	Bit 14: Chopper mode (0=SpreadCycle, 1=Constant off time) More...

uint32_t tbl: 2
	Bits 16..15: Comparator blank time select. More...

uint32_t reserved2: 1
	Bit 17: Reserved, set to 0. More...

uint32_t vhighfs: 1
	Bit 18: High velocity fullstep selection. More...

uint32_t vhighchm: 1
	Bit 19: High velocity chopper mode. More...

uint32_t tpfd: 4
	Bits 23..20: Passive fast decay time. More...

uint32_t mres: 4
	Bits 27..24: Micro step resolution. More...

uint32_t intpol: 1
	Bit 28: Interpolation to 256 microsteps. More...

uint32_t dedge: 1
	Bit 29: Enable double edge step pulses. More...

uint32_t diss2g: 1
	Bit 30: Short to GND protection disable. More...

uint32_t diss2vs: 1
	Bit 31: Short to supply protection disable. More...

}	bits

Detailed Description

Chopper and driver configuration register (CHOPCONF)

Configuration for chopper timing, microstep resolution, and driver operation modes.

Bit assignments per datasheet:

Bits 3..0: toff3..toff0 - Off time and driver enable (4 bits) %0000: Driver disable, all bridges off %0001: 1 – use only with TBL ≥ 2 %0010...%1111: 2 ... 15
Bits 6..4: hstrt2..hstrt0/TFD[2..0] - Hysteresis start value (chm=0) or fast decay time setting (chm=1) (3 bits) chm=0: %000...%111: Add 1, 2, ..., 8 to hysteresis low value HEND chm=1: Fast decay time setting TFD (MSB: fd3)
Bits 10..7: hend3..hend0/HEND/OFFSET - Hysteresis low value (chm=0) or sine wave offset (chm=1) (4 bits) chm=0: %0000...%1111: Hysteresis is -3, -2, -1, 0, 1, ..., 12 chm=1: %0000...%1111: Offset is -3, -2, -1, 0, 1, ..., 12
Bit 11: fd3/TFD[3] - MSB of fast decay time setting (chm=1) or reserved (chm=0)
Bit 12: disfdcc - Fast decay mode (chm=1: disables current comparator usage for termination of fast decay cycle)
Bit 13: Reserved, set to 0
Bit 14: chm - Chopper mode (0=Standard SpreadCycle, 1=Constant off time with fast decay time)
Bits 16..15: tbl1..tbl0 - Blank time select (2 bits) %00...%11: Set comparator blank time to 16, 24, 36 or 54 clocks
Bit 17: Reserved, set to 0
Bit 18: vhighfs - High velocity fullstep selection (enables switching to fullstep when VHIGH is exceeded)
Bit 19: vhighchm - High velocity chopper mode (enables switching to chm=1 and fd=0 when VHIGH is exceeded)
Bits 23..20: tpfd3..tpfd0 - Passive fast decay time (4 bits) %0000: Disable %0001...%1111: 1 ... 15
Bits 27..24: mres3..mres0 - Micro step resolution (4 bits) %0000: Native 256 microstep setting %0001...%1000: 128, 64, 32, 16, 8, 4, 2, FULLSTEP
Bit 28: intpol - Interpolation to 256 microsteps (1: extrapolates MRES to 256 microsteps)
Bit 29: dedge - Enable double edge step pulses (1: enables step impulse at each step edge)
Bit 30: diss2g - Short to GND protection disable (1: disables protection)
Bit 31: diss2vs - Short to supply protection disable (1: disables protection)

Member Data Documentation

◆ [struct]

struct { ... } tmc51x0::CHOPCONF_Register::bits

◆ chm

uint32_t tmc51x0::CHOPCONF_Register::chm

Bit 14: Chopper mode (0=SpreadCycle, 1=Constant off time)

◆ dedge

uint32_t tmc51x0::CHOPCONF_Register::dedge

Bit 29: Enable double edge step pulses.

◆ disfdcc

uint32_t tmc51x0::CHOPCONF_Register::disfdcc

Bit 12: Fast decay mode (chm=1)

◆ diss2g

uint32_t tmc51x0::CHOPCONF_Register::diss2g

Bit 30: Short to GND protection disable.

◆ diss2vs

uint32_t tmc51x0::CHOPCONF_Register::diss2vs

Bit 31: Short to supply protection disable.

◆ hend_offset

uint32_t tmc51x0::CHOPCONF_Register::hend_offset

Bits 10..7: HEND (chm=0) or OFFSET (chm=1)

◆ hstrt_tfd

uint32_t tmc51x0::CHOPCONF_Register::hstrt_tfd

Bits 6..4: HSTRT (chm=0) or TFD[2..0] (chm=1)

◆ intpol

uint32_t tmc51x0::CHOPCONF_Register::intpol

Bit 28: Interpolation to 256 microsteps.

◆ mres

uint32_t tmc51x0::CHOPCONF_Register::mres

Bits 27..24: Micro step resolution.

◆ reserved1

uint32_t tmc51x0::CHOPCONF_Register::reserved1

Bit 13: Reserved, set to 0.

◆ reserved2

uint32_t tmc51x0::CHOPCONF_Register::reserved2

Bit 17: Reserved, set to 0.

◆ tbl

uint32_t tmc51x0::CHOPCONF_Register::tbl

Bits 16..15: Comparator blank time select.

◆ tfd_3

uint32_t tmc51x0::CHOPCONF_Register::tfd_3

Bit 11: TFD[3] (chm=1) or reserved (chm=0)

◆ toff

uint32_t tmc51x0::CHOPCONF_Register::toff

Bits 3..0: Off time and driver enable.

◆ tpfd

uint32_t tmc51x0::CHOPCONF_Register::tpfd

Bits 23..20: Passive fast decay time.

◆ value

uint32_t tmc51x0::CHOPCONF_Register::value

◆ vhighchm

uint32_t tmc51x0::CHOPCONF_Register::vhighchm

Bit 19: High velocity chopper mode.

◆ vhighfs

uint32_t tmc51x0::CHOPCONF_Register::vhighfs

Bit 18: High velocity fullstep selection.

The documentation for this union was generated from the following file:

tmc51x0_registers.hpp

Public Attributes