tmc51x0_registers.hpp

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#pragma once
#include "tmc51x0_register_defs.hpp"
#include <cstdint>
 
namespace tmc51x0 {
 
namespace Registers {
// NOLINTNEXTLINE(cppcoreguidelines-macro-usage) - Intentional: X-macro pattern
// for register definitions
#define X(addr, name, access, category, desc) constexpr uint8_t name = addr;
REGISTER_LIST(X)
#undef X
} // namespace Registers
 
enum class RampMode : uint8_t {
  POSITIONING = 0x00,  
  VELOCITY_POS = 0x01, 
  VELOCITY_NEG = 0x02, 
  HOLD = 0x03          
};
 
enum class PWMFreewheel : uint8_t {
  NORMAL = 0x00,   
  ENABLED = 0x01,  
  SHORT_LS = 0x02, 
  SHORT_HS = 0x03  
};
 
enum class EncoderSensitivity : uint8_t {
  NO_EDGE = 0x00,      
  RISING_EDGE = 0x01,  
  FALLING_EDGE = 0x02, 
  BOTH_EDGES =
      0x03 
};
 
union GCONF_Register {
  uint32_t value;
 
  struct {
    uint32_t
        recalibrate : 1; 
    uint32_t faststandstill : 1; 
    uint32_t en_pwm_mode : 1; 
    uint32_t multistep_filt : 1; 
    uint32_t shaft : 1;       
    uint32_t diag0_error : 1; 
    uint32_t
        diag0_otpw : 1; 
    uint32_t
        diag0_stall_step : 1; 
    uint32_t
        diag1_stall_dir : 1; 
    uint32_t diag1_index : 1; 
    uint32_t
        diag1_onstate : 1; 
    uint32_t diag1_steps_skipped : 1; 
    uint32_t
        diag0_int_pushpull : 1; 
    uint32_t diag1_poscomp_pushpull : 1; 
    uint32_t small_hysteresis : 1; 
    uint32_t
        stop_enable : 1; 
    uint32_t direct_mode : 1; 
    uint32_t test_mode : 1; 
    uint32_t reserved : 14; 
  } bits;
};
 
union GSTAT_Register {
  uint32_t value;
 
  struct {
    uint32_t reset : 1; 
    uint32_t drv_err : 1; 
    uint32_t uv_cp : 1;   
    uint32_t reserved : 29; 
  } bits;
};
 
union NODECONF_Register {
  uint32_t value;
 
  struct {
    uint32_t nodeaddr : 8; 
    uint32_t
        senddelay : 4; 
    uint32_t reserved : 20; 
  } bits;
};
 
union IOIN_Register {
  uint32_t value;
 
  struct {
    uint32_t refl_step : 1;      
    uint32_t refr_dir : 1;       
    uint32_t encb_dcen_cfg4 : 1; 
    uint32_t enca_dcin_cfg5 : 1; 
    uint32_t drv_enn : 1;        
    uint32_t enc_n_dco_cfg6 : 1; 
    uint32_t sd_mode : 1;        
    uint32_t swcomp_in : 1;      
    uint32_t reserved : 16;      
    uint32_t version : 8;        
  } bits;
};
 
union OTP_PROG_Register {
  uint32_t value;
 
  struct {
    uint32_t otpbit : 3; 
    uint32_t reserved1 : 1;  
    uint32_t otpbyte : 2;    
    uint32_t reserved2 : 2;  
    uint32_t otpmagic : 8;   
    uint32_t reserved3 : 16; 
  } bits;
};
 
union OTP_READ_Register {
  uint32_t value;
 
  struct {
    uint32_t otp_fclktrim : 5; 
    uint32_t
        otp_S2_level : 1;   
    uint32_t otp_bbm : 1;   
    uint32_t otp_tbl : 1;   
    uint32_t reserved : 24; 
  } bits;
};
 
union SHORT_CONF_Register {
  uint32_t value;
 
  struct {
    uint32_t s2vs_level : 4; 
    uint32_t reserved1 : 4; 
    uint32_t s2g_level : 4; 
    uint32_t reserved2 : 4;   
    uint32_t shortfilter : 2; 
    uint32_t shortdelay : 1; 
    uint32_t reserved3 : 13; 
  } bits;
};
 
union DRV_CONF_Register {
  uint32_t value;
 
  struct {
    uint32_t bbmtime : 5; 
    uint32_t reserved1 : 3; 
    uint32_t
        bbmclks : 4; 
    uint32_t reserved2 : 4; 
    uint32_t otselect : 2; 
    uint32_t drvstrength : 2; 
    uint32_t filt_isense : 2; 
    uint32_t reserved3 : 10;  
  } bits;
};
 
union OFFSET_READ_Register {
  uint32_t value;
 
  struct {
    uint32_t
        phase_b : 8; 
    uint32_t
        phase_a : 8; 
    uint32_t reserved : 16; 
  } bits;
};
 
union IHOLD_IRUN_Register {
  uint32_t value;
 
  struct {
    uint32_t ihold : 5; 
    uint32_t reserved1 : 3; 
    uint32_t irun : 5; 
    uint32_t reserved2 : 3;  
    uint32_t iholddelay : 4; 
    uint32_t reserved3 : 12; 
  } bits;
};
 
union SW_MODE_Register {
  uint32_t value;
 
  struct {
    uint32_t stop_l_enable : 1; 
    uint32_t stop_r_enable : 1; 
    uint32_t pol_stop_l : 1; 
    uint32_t
        pol_stop_r : 1; 
    uint32_t
        swap_lr : 1; 
    uint32_t latch_l_active : 1; 
    uint32_t
        latch_l_inactive : 1; 
    uint32_t latch_r_active : 1; 
    uint32_t
        latch_r_inactive : 1; 
    uint32_t en_latch_encoder : 1; 
    uint32_t sg_stop : 1;     
    uint32_t en_softstop : 1; 
    uint32_t reserved : 20;   
  } bits;
};
 
union RAMP_STAT_Register {
  uint32_t value;
 
  struct {
    uint32_t status_stop_l : 1;  
    uint32_t status_stop_r : 1;  
    uint32_t status_latch_l : 1; 
    uint32_t status_latch_r : 1; 
    uint32_t event_stop_l : 1; 
    uint32_t event_stop_r : 1; 
    uint32_t event_stop_sg : 1; 
    uint32_t event_pos_reached : 1; 
    uint32_t
        velocity_reached : 1; 
    uint32_t
        position_reached : 1; 
    uint32_t vzero : 1;       
    uint32_t t_zerowait_active : 1; 
    uint32_t second_move : 1; 
    uint32_t status_sg : 1;   
    uint32_t reserved : 18;   
  } bits;
};
 
union ENCMODE_Register {
  uint32_t value;
 
  struct {
    uint32_t pol_A : 1; 
    uint32_t pol_B : 1; 
    uint32_t pol_N : 1; 
    uint32_t
        ignore_AB : 1; 
    uint32_t clr_cont : 1; 
    uint32_t clr_once : 1; 
    uint32_t
        pos_edge : 1; 
    uint32_t
        neg_edge : 1; 
    uint32_t clr_enc_x : 1; 
    uint32_t latch_x_act : 1; 
    uint32_t enc_sel_decimal : 1; 
    uint32_t reserved : 21;       
  } bits;
};
 
union ENC_STATUS_Register {
  uint32_t value;
 
  struct {
    uint32_t n_event : 1; 
    uint32_t deviation_warn : 1; 
    uint32_t reserved : 30; 
  } bits;
};
 
union MSLUTSEL_Register {
  uint32_t value;
 
  struct {
    uint32_t w0 : 2; 
    uint32_t w1 : 2; 
    uint32_t w2 : 2; 
    uint32_t w3 : 2; 
    uint32_t x1 : 8; 
    uint32_t x2 : 8; 
    uint32_t x3 : 8; 
  } bits;
};
 
union MSCURACT_Register {
  uint32_t value;
 
  struct {
    int32_t cur_b : 9; 
    uint32_t reserved1 : 7; 
    int32_t cur_a : 9;      
    uint32_t reserved2 : 7; 
  } bits;
};
 
union CHOPCONF_Register {
  uint32_t value;
 
  struct {
    uint32_t toff : 4;        
    uint32_t hstrt_tfd : 3;   
    uint32_t hend_offset : 4; 
    uint32_t tfd_3 : 1;       
    uint32_t disfdcc : 1;     
    uint32_t reserved1 : 1;   
    uint32_t
        chm : 1; 
    uint32_t tbl : 2;       
    uint32_t reserved2 : 1; 
    uint32_t vhighfs : 1;   
    uint32_t vhighchm : 1;  
    uint32_t tpfd : 4;      
    uint32_t mres : 4;      
    uint32_t intpol : 1;    
    uint32_t dedge : 1;     
    uint32_t diss2g : 1;    
    uint32_t diss2vs : 1;   
  } bits;
};
 
union COOLCONF_Register {
  uint32_t value;
 
  struct {
    uint32_t semin : 4;     
    uint32_t reserved1 : 1; 
    uint32_t seup : 2;      
    uint32_t reserved2 : 1; 
    uint32_t semax : 4; 
    uint32_t reserved3 : 1; 
    uint32_t sedn : 2;      
    uint32_t seimin : 1; 
    int32_t sgt : 7; 
    uint32_t reserved4 : 1; 
    uint32_t sfilt : 1;     
    uint32_t reserved5 : 7; 
  } bits;
};
 
union DCCTRL_Register {
  uint32_t value;
 
  struct {
    uint32_t dc_time : 10;  
    uint32_t reserved1 : 6; 
    uint32_t dc_sg : 8;     
    uint32_t reserved2 : 8; 
  } bits;
};
 
union DRV_STATUS_Register {
  uint32_t value;
 
  struct {
    uint32_t sg_result : 10; 
    uint32_t reserved1 : 2;  
    uint32_t s2vsa : 1;      
    uint32_t s2vsb : 1;      
    uint32_t stealth : 1;    
    uint32_t fsactive : 1;   
    uint32_t cs_actual : 5;  
    uint32_t reserved2 : 3;  
    uint32_t stallguard : 1; 
    uint32_t ot : 1;         
    uint32_t otpw : 1;       
    uint32_t s2ga : 1;       
    uint32_t s2gb : 1;       
    uint32_t ola : 1;        
    uint32_t olb : 1;        
    uint32_t stst : 1;       
  } bits;
};
 
union PWMCONF_Register {
  uint32_t value;
 
  struct {
    uint32_t pwm_ofs : 8; 
    uint32_t
        pwm_grad : 8; 
    uint32_t pwm_freq : 2; 
    uint32_t
        pwm_autoscale : 1; 
    uint32_t pwm_autograd : 1; 
    uint32_t freewheel : 2; 
    uint32_t reserved1 : 2; 
    uint32_t pwm_reg : 4;   
    uint32_t pwm_lim : 4; 
  } bits;
};
 
union PWM_SCALE_Register {
  uint32_t value;
 
  struct {
    uint32_t pwm_scale_sum : 8; 
    uint32_t reserved1 : 8;     
    int32_t pwm_scale_auto : 9; 
    uint32_t reserved2 : 7; 
  } bits;
};
 
union PWM_AUTO_Register {
  uint32_t value;
 
  struct {
    uint32_t pwm_ofs_auto : 8;  
    uint32_t reserved1 : 8;     
    uint32_t pwm_grad_auto : 8; 
    uint32_t reserved2 : 8;     
  } bits;
};
 
} // namespace tmc51x0