tmc51x0::ENCMODE_Register Union Reference

Encoder configuration register (ENCMODE) More...

#include <tmc51x0_registers.hpp>

Public Attributes
uint32_t	value
struct {
uint32_t   pol_A: 1
uint32_t   pol_B: 1
uint32_t   pol_N: 1
uint32_t   ignore_AB: 1
	Bit 3: Ignore A and B polarity for N channel event. More...
uint32_t   clr_cont: 1
uint32_t   clr_once: 1
uint32_t   pos_edge: 1
	Bit 6: N channel event sensitivity (positive edge) More...
uint32_t   neg_edge: 1
	Bit 7: N channel event sensitivity (negative edge) More...
uint32_t   clr_enc_x: 1
	Bit 8: Clear encoder counter X_ENC upon N-event. More...
uint32_t   latch_x_act: 1
uint32_t   enc_sel_decimal: 1
uint32_t   reserved: 21
	Reserved bits (11..31) More...
}	bits

Detailed Description

Encoder configuration register (ENCMODE)

Configuration for encoder interface and N channel event handling.

Bit assignments per datasheet:

• Bit 0: pol_A - Required A polarity for an N channel event (0=neg., 1=pos.)
• Bit 1: pol_B - Required B polarity for an N channel event (0=neg., 1=pos.)
• Bit 2: pol_N - Defines active polarity of N (0=low active, 1=high active)
• Bit 3: ignore_AB - Ignore A and B polarity for N channel event (0: N event occurs only when polarities given by pol_N, pol_A and pol_B match) (1: Ignore A and B polarity for N channel event)
• Bit 4: clr_cont - Always latch or latch and clear X_ENC upon an N event
• Bit 5: clr_once - Latch or latch and clear X_ENC on the next N event following the write access
• Bit 6: pos_edge - N channel event sensitivity (positive edge)
• Bit 7: neg_edge - N channel event sensitivity (negative edge) Sensitivity encoding:
  • 00: N channel event is active during an active N event level
  • 01: N channel is valid upon active going N event
  • 10: N channel is valid upon inactive going N event
  • 11: N channel is valid upon active going and inactive going N event
• Bit 8: clr_enc_x - Clear encoder counter X_ENC upon N-event (0: Upon N event, X_ENC becomes latched to ENC_LATCH only) (1: Latch and additionally clear encoder counter X_ENC at N-event)
• Bit 9: latch_x_act - Also latch XACTUAL position together with X_ENC
• Bit 10: enc_sel_decimal - Encoder prescaler divisor (0: Binary mode - Counts ENC_CONST(fractional part) /65536) (1: Decimal mode - Counts in ENC_CONST(fractional part) /10000)

Member Data Documentation

[struct]

struct { ... } tmc51x0::ENCMODE_Register::bits

clr_cont

uint32_t tmc51x0::ENCMODE_Register::clr_cont

Bit 4: Always latch or latch and clear X_ENC upon an N event

clr_enc_x

uint32_t tmc51x0::ENCMODE_Register::clr_enc_x

Bit 8: Clear encoder counter X_ENC upon N-event.

clr_once

uint32_t tmc51x0::ENCMODE_Register::clr_once

Bit 5: Latch or latch and clear X_ENC on the next N event following the write access

enc_sel_decimal

uint32_t tmc51x0::ENCMODE_Register::enc_sel_decimal

Bit 10: Encoder prescaler divisor (0=binary, 1=decimal)

ignore_AB

uint32_t tmc51x0::ENCMODE_Register::ignore_AB

Bit 3: Ignore A and B polarity for N channel event.

latch_x_act

uint32_t tmc51x0::ENCMODE_Register::latch_x_act

Bit 9: Also latch XACTUAL position together with X_ENC

neg_edge

uint32_t tmc51x0::ENCMODE_Register::neg_edge

Bit 7: N channel event sensitivity (negative edge)

pol_A

uint32_t tmc51x0::ENCMODE_Register::pol_A

Bit 0: Required A polarity for an N channel event (0=neg., 1=pos.)

pol_B

uint32_t tmc51x0::ENCMODE_Register::pol_B

Bit 1: Required B polarity for an N channel event (0=neg., 1=pos.)

pol_N

uint32_t tmc51x0::ENCMODE_Register::pol_N

Bit 2: Defines active polarity of N (0=low active, 1=high active)

pos_edge

uint32_t tmc51x0::ENCMODE_Register::pos_edge

Bit 6: N channel event sensitivity (positive edge)

reserved

uint32_t tmc51x0::ENCMODE_Register::reserved

Reserved bits (11..31)

value

uint32_t tmc51x0::ENCMODE_Register::value

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The documentation for this union was generated from the following file:

• tmc51x0_registers.hpp