|
HF-TMC51x0 Driver (TMC5130 & TMC5160) 0.1.0-dev
Hardware Agnostic C++ Driver for the TMC51x0 (TMC5130 & TMC5160)
|
General configuration register (GCONF) More...
#include <tmc51x0_registers.hpp>
Public Attributes | ||
| uint32_t | value | |
| struct { | ||
| uint32_t recalibrate: 1 | ||
| uint32_t faststandstill: 1 | ||
| uint32_t en_pwm_mode: 1 | ||
| uint32_t multistep_filt: 1 | ||
| uint32_t shaft: 1 | ||
| Bit 4: 1=Inverse motor direction. More... | ||
| uint32_t diag0_error: 1 | ||
| uint32_t diag0_otpw: 1 | ||
| uint32_t diag0_stall_step: 1 | ||
| uint32_t diag1_stall_dir: 1 | ||
| uint32_t diag1_index: 1 | ||
| uint32_t diag1_onstate: 1 | ||
| uint32_t diag1_steps_skipped: 1 | ||
| uint32_t diag0_int_pushpull: 1 | ||
| uint32_t diag1_poscomp_pushpull: 1 | ||
| uint32_t small_hysteresis: 1 | ||
| uint32_t stop_enable: 1 | ||
| uint32_t direct_mode: 1 | ||
| uint32_t test_mode: 1 | ||
| uint32_t reserved: 14 | ||
| Bits 18-31: Reserved. More... | ||
| } | bits | |
General configuration register (GCONF)
Global configuration flags for the TMC5160 driver.
Bit assignments per datasheet:
| struct { ... } tmc51x0::GCONF_Register::bits |
| uint32_t tmc51x0::GCONF_Register::diag0_error |
Bit 5: (only with SD_MODE=1) 1=Enable DIAG0 active on driver errors (OT, S2G, UV_CP). DIAG0 always shows reset-status.
| uint32_t tmc51x0::GCONF_Register::diag0_int_pushpull |
Bit 12: SWN_DIAG0 output: 0=open collector (active low), 1=push pull (active high)
| uint32_t tmc51x0::GCONF_Register::diag0_otpw |
Bit 6: (only with SD_MODE=1) 1=Enable DIAG0 active on driver over temperature prewarning (otpw)
| uint32_t tmc51x0::GCONF_Register::diag0_stall_step |
Bit 7: (SD_MODE=1) 1=Enable DIAG0 active on motor stall (set TCOOLTHRS before using). (SD_MODE=0) 0=DIAG0 outputs interrupt signal, 1=Enable DIAG0 as STEP output (half frequency, dual edge triggered)
| uint32_t tmc51x0::GCONF_Register::diag1_index |
Bit 9: (only with SD_MODE=1) 1=Enable DIAG1 active on index position (microstep look up table position 0)
| uint32_t tmc51x0::GCONF_Register::diag1_onstate |
Bit 10: (only with SD_MODE=1) 1=Enable DIAG1 active when chopper is on (for the coil which is in the second half of the fullstep)
| uint32_t tmc51x0::GCONF_Register::diag1_poscomp_pushpull |
Bit 13: SWP_DIAG1 output: 0=open collector (active low), 1=push pull (active high)
| uint32_t tmc51x0::GCONF_Register::diag1_stall_dir |
Bit 8: (SD_MODE=1) 1=Enable DIAG1 active on motor stall (set TCOOLTHRS before using). (SD_MODE=0) 0=DIAG1 outputs position compare signal, 1=Enable DIAG1 as DIR output
| uint32_t tmc51x0::GCONF_Register::diag1_steps_skipped |
Bit 11: (only with SD_MODE=1) 1=Enable output toggle when steps are skipped in DcStep mode (increment of LOST_STEPS). Do not enable in conjunction with other DIAG1 options.
| uint32_t tmc51x0::GCONF_Register::direct_mode |
Bit 16: 0=Normal operation, 1=Direct motor coil control: XTARGET bits 8..0=coil A current, bits 24..16=coil B current (scaled by IHOLD). Velocity based current regulation of StealthChop not available.
| uint32_t tmc51x0::GCONF_Register::en_pwm_mode |
Bit 2: 1=StealthChop voltage PWM mode enabled (depending on velocity thresholds). Switch only in stand-still at IHOLD=nominal IRUN.
| uint32_t tmc51x0::GCONF_Register::faststandstill |
Bit 1: Standstill timeout: 1=Short time (2^18 clocks), 0=Normal time (2^20 clocks)
| uint32_t tmc51x0::GCONF_Register::multistep_filt |
Bit 3: 1=Enable step input filtering for StealthChop optimization with external step source (default=1)
| uint32_t tmc51x0::GCONF_Register::recalibrate |
Bit 0: 1=Zero crossing recalibration during driver disable (via DRV_ENN or via TOFF setting)
| uint32_t tmc51x0::GCONF_Register::reserved |
Bits 18-31: Reserved.
| uint32_t tmc51x0::GCONF_Register::shaft |
Bit 4: 1=Inverse motor direction.
| uint32_t tmc51x0::GCONF_Register::small_hysteresis |
Bit 14: Step frequency comparison hysteresis: 0=1/16, 1=1/32
| uint32_t tmc51x0::GCONF_Register::stop_enable |
Bit 15: 0=Normal operation, 1=Emergency stop: ENCA_DCIN stops the sequencer when tied high (no steps become executed, motor goes to standstill)
| uint32_t tmc51x0::GCONF_Register::test_mode |
Bit 17: 0=Normal operation, 1=Enable analog test output on pin ENCN_DCO. IHOLD[1..0] selects function (0..2: T120, DAC, VDDH). Hint: Not for user, set to 0!
| uint32_t tmc51x0::GCONF_Register::value |