tmc51x0::MSLUTSEL_Register Union Reference

Microstep lookup table segmentation definition register (MSLUTSEL) More...

#include <tmc51x0_registers.hpp>

Public Attributes
uint32_t	value
struct {
uint32_t   w0: 2
	Bits 1..0: LUT width select from ofs00 to ofs(X1-1) More...
uint32_t   w1: 2
	Bits 3..2: LUT width select from ofs(X1) to ofs(X2-1) More...
uint32_t   w2: 2
	Bits 5..4: LUT width select from ofs(X2) to ofs(X3-1) More...
uint32_t   w3: 2
	Bits 7..6: LUT width select from ofs(X3) to ofs255. More...
uint32_t   x1: 8
	Bits 15..8: LUT segment 1 start. More...
uint32_t   x2: 8
	Bits 23..16: LUT segment 2 start. More...
uint32_t   x3: 8
	Bits 31..24: LUT segment 3 start. More...
}	bits

Detailed Description

Microstep lookup table segmentation definition register (MSLUTSEL)

Defines four segments within each quarter MSLUT wave and their width control.

Bit assignments per datasheet:

• Bits 1..0: W0 - LUT width select from ofs00 to ofs(X1-1)
• Bits 3..2: W1 - LUT width select from ofs(X1) to ofs(X2-1)
• Bits 5..4: W2 - LUT width select from ofs(X2) to ofs(X3-1)
• Bits 7..6: W3 - LUT width select from ofs(X3) to ofs255
• Bits 15..8: X1 - LUT segment 1 start
• Bits 23..16: X2 - LUT segment 2 start
• Bits 31..24: X3 - LUT segment 3 start

Width control bit coding W0...W3:

• %00: MSLUT entry 0, 1 select: -1, +0
• %01: MSLUT entry 0, 1 select: +0, +1
• %10: MSLUT entry 0, 1 select: +1, +2
• %11: MSLUT entry 0, 1 select: +2, +3

Segment boundaries:

• Segment 0: 0 to X1-1
• Segment 1: X1 to X2-1
• Segment 2: X2 to X3-1
• Segment 3: X3 to 255

For defined response: 0 < X1 < X2 < X3

Member Data Documentation

[struct]

struct { ... } tmc51x0::MSLUTSEL_Register::bits

value

uint32_t tmc51x0::MSLUTSEL_Register::value

w0

uint32_t tmc51x0::MSLUTSEL_Register::w0

Bits 1..0: LUT width select from ofs00 to ofs(X1-1)

w1

uint32_t tmc51x0::MSLUTSEL_Register::w1

Bits 3..2: LUT width select from ofs(X1) to ofs(X2-1)

w2

uint32_t tmc51x0::MSLUTSEL_Register::w2

Bits 5..4: LUT width select from ofs(X2) to ofs(X3-1)

w3

uint32_t tmc51x0::MSLUTSEL_Register::w3

Bits 7..6: LUT width select from ofs(X3) to ofs255.

x1

uint32_t tmc51x0::MSLUTSEL_Register::x1

Bits 15..8: LUT segment 1 start.

x2

uint32_t tmc51x0::MSLUTSEL_Register::x2

Bits 23..16: LUT segment 2 start.

x3

uint32_t tmc51x0::MSLUTSEL_Register::x3

Bits 31..24: LUT segment 3 start.

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The documentation for this union was generated from the following file:

• tmc51x0_registers.hpp