OTP read register (OTP_READ) More...

#include <tmc51x0_registers.hpp>

Public Attributes
uint32_t	value

struct {

uint32_t otp_fclktrim: 5
	Bits 4..0: Reset default for FCLKTRIM (0-31) More...

uint32_t otp_S2_level: 1
	Bit 5: Reset default for Short detection levels. More...

uint32_t otp_bbm: 1
	Bit 6: Reset default for DRVCONF.BBMCLKS. More...

uint32_t otp_tbl: 1
	Bit 7: Reset default for TBL. More...

uint32_t reserved: 24
	Reserved bits. More...

}	bits

Detailed Description

OTP read register (OTP_READ)

One-time programmable configuration memory read register.

OTP memory holds power-up defaults for certain registers. All OTP bits are cleared to 0 by default. Programming can only set bits, clearing is not possible.

Bit assignments per datasheet OTP memory map:

Bit 7 (otp0.7): otp_TBL - Reset default for TBL (0: TBL=%10 ~3μs, 1: TBL=%01 ~2μs)
Bit 6 (otp0.6): otp_BBM - Reset default for DRVCONF.BBMCLKS (0: BBMCLKS=4, 1: BBMCLKS=2)
Bit 5 (otp0.5): otp_S2_LEVEL - Reset default for short-detection levels (0: S2G_LEVEL=S2VS_LEVEL=6, 1: S2G_LEVEL=S2VS_LEVEL=12)
Bits 4..0 (otp0.4..0): OTP_FCLKTRIM - Reset default for FCLKTRIM (0: lowest frequency, 31: highest frequency) Factory pre-programmed to 12MHz, differs between ICs!

Member Data Documentation

◆ [struct]

struct { ... } tmc51x0::OTP_READ_Register::bits

◆ otp_bbm

uint32_t tmc51x0::OTP_READ_Register::otp_bbm

Bit 6: Reset default for DRVCONF.BBMCLKS.

◆ otp_fclktrim

uint32_t tmc51x0::OTP_READ_Register::otp_fclktrim

Bits 4..0: Reset default for FCLKTRIM (0-31)

◆ otp_S2_level

uint32_t tmc51x0::OTP_READ_Register::otp_S2_level

Bit 5: Reset default for Short detection levels.

◆ otp_tbl

uint32_t tmc51x0::OTP_READ_Register::otp_tbl

Bit 7: Reset default for TBL.

◆ reserved

uint32_t tmc51x0::OTP_READ_Register::reserved

Reserved bits.

◆ value

uint32_t tmc51x0::OTP_READ_Register::value

The documentation for this union was generated from the following file:

tmc51x0_registers.hpp

Public Attributes