HF-TMC9660 Driver 0.1.0-dev
Hardware Agnostic C++ Driver for the TMC9660
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tmc9660_mcc.hpp
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1#pragma once
2#include <cstdint>
8namespace tmc9660 {
9namespace register_mode {
10namespace MCC {
11
25struct CHIP_ID {
26 static constexpr uint16_t ADDRESS = 0x000;
27 union {
28 uint32_t value;
29 struct {
30 uint32_t ID : 32;
31 } bits;
32 };
33};
34
51struct I1_I0_RAW {
52 static constexpr uint16_t ADDRESS = 0x020;
53 union {
54 uint32_t value;
55 struct {
56 int16_t I1 : 16;
57 int16_t I0 : 16;
58 } bits;
59 };
60};
61
77struct I3_I2_RAW {
78 static constexpr uint16_t ADDRESS = 0x021;
79 union {
80 uint32_t value;
81 struct {
82 int16_t I3 : 16;
83 int16_t I2 : 16;
84 } bits;
85 };
86};
87
102struct U1_U0_RAW {
103 static constexpr uint16_t ADDRESS = 0x022;
104 union {
105 uint32_t value;
106 struct {
107 int16_t U1 : 16;
108 int16_t U0 : 16;
109 } bits;
110 };
111};
112
127struct U3_U2_RAW {
128 static constexpr uint16_t ADDRESS = 0x023;
129 union {
130 uint32_t value;
131 struct {
132 int16_t U3 : 16;
133 int16_t U2 : 16;
134 } bits;
135 };
136};
137
153struct TEMP_VM_RAW {
154 static constexpr uint16_t ADDRESS = 0x024;
155 union {
156 uint32_t value;
157 struct {
158 int16_t TEMP : 16;
159 uint16_t VM : 16;
160 } bits;
161 };
162};
163
178struct AIN1_AIN0_RAW {
179 static constexpr uint16_t ADDRESS = 0x025;
180 union {
181 uint32_t value;
182 struct {
183 uint16_t AIN1 : 16;
184 uint16_t AIN0 : 16;
185 } bits;
186 };
187};
188
203struct AIN3_AIN2_RAW {
204 static constexpr uint16_t ADDRESS = 0x026;
205 union {
206 uint32_t value;
207 struct {
208 uint16_t AIN3 : 16;
209 uint16_t AIN2 : 16;
210 } bits;
211 };
212};
213
253struct I_GEN_CONFIG {
254 static constexpr uint16_t ADDRESS = 0x040;
255 union {
256 uint32_t value;
257 struct {
258 uint32_t UX1_SELECT : 2;
259 uint32_t VX2_SELECT : 2;
260 uint32_t WY1_SELECT : 2;
261 uint32_t Y2_SELECT : 2;
262 uint32_t : 1;
263 uint32_t MEASUREMENT_MODE : 3;
264 uint32_t : 3;
265 uint32_t TRIGGER_SELECT : 1;
266 uint32_t : 3;
267 uint32_t TRIGGER_POS : 16;
268 } bits;
269 };
270};
271
286struct I0_CONFIG {
287 static constexpr uint16_t ADDRESS = 0x041;
288 union {
289 uint32_t value;
290 struct {
291 int16_t OFFSET;
292 int16_t SCALE;
293 } bits;
294 };
295};
296
311struct I1_CONFIG {
312 static constexpr uint16_t ADDRESS = 0x042;
313 union {
314 uint32_t value;
315 struct {
316 int16_t OFFSET;
317 int16_t SCALE;
318 } bits;
319 };
320};
321
336struct I2_CONFIG {
337 static constexpr uint16_t ADDRESS = 0x043;
338 union {
339 uint32_t value;
340 struct {
341 int16_t OFFSET;
342 int16_t SCALE;
343 } bits;
344 };
345};
346
361struct I3_CONFIG {
362 static constexpr uint16_t ADDRESS = 0x044;
363 union {
364 uint32_t value;
365 struct {
366 int16_t OFFSET;
367 int16_t SCALE;
368 } bits;
369 };
370};
371
386struct I1_I0_SCALED {
387 static constexpr uint16_t ADDRESS = 0x045;
388 union {
389 uint32_t value;
390 struct {
391 int16_t I1 : 16;
392 int16_t I0 : 16;
393 } bits;
394 };
395};
396
411struct I3_I2_SCALED {
412 static constexpr uint16_t ADDRESS = 0x046;
413 union {
414 uint32_t value;
415 struct {
416 int16_t I3 : 16;
417 int16_t I2 : 16;
418 } bits;
419 };
420};
421
436struct IWY_IUX {
437 static constexpr uint16_t ADDRESS = 0x047;
438 union {
439 uint32_t value;
440 struct {
441 int16_t IWY : 16;
442 int16_t IUX : 16;
443 } bits;
444 };
445};
446
460struct IV_RAW {
461 static constexpr uint16_t ADDRESS = 0x048;
462 union {
463 uint32_t value;
464 struct {
465 int16_t IV : 16;
466 uint16_t : 16;
467 } bits;
468 };
469};
470
512struct STATUS {
513 static constexpr uint16_t ADDRESS = 0x049;
514 union {
515 uint32_t value;
516 struct {
517 uint32_t I0_CLIPPED : 1;
518 uint32_t I1_CLIPPED : 1;
519 uint32_t I2_CLIPPED : 1;
520 uint32_t I3_CLIPPED : 1;
521 uint32_t U0_CLIPPED : 1;
522 uint32_t U1_CLIPPED : 1;
523 uint32_t U2_CLIPPED : 1;
524 uint32_t U3_CLIPPED : 1;
525 uint32_t AIN0_CLIPPED : 1;
526 uint32_t AIN1_CLIPPED : 1;
527 uint32_t AIN2_CLIPPED : 1;
528 uint32_t AIN3_CLIPPED : 1;
529 uint32_t VM_CLIPPED : 1;
530 uint32_t TEMP_CLIPPED : 1;
531 uint32_t : 2;
532 uint32_t I0_DONE : 1;
533 uint32_t I1_DONE : 1;
534 uint32_t I2_DONE : 1;
535 uint32_t I3_DONE : 1;
536 uint32_t U0_DONE : 1;
537 uint32_t U1_DONE : 1;
538 uint32_t U2_DONE : 1;
539 uint32_t U3_DONE : 1;
540 uint32_t AIN0_DONE : 1;
541 uint32_t AIN1_DONE : 1;
542 uint32_t AIN2_DONE : 1;
543 uint32_t AIN3_DONE : 1;
544 uint32_t VM_DONE : 1;
545 uint32_t TEMP_DONE : 1;
546 } bits;
547 };
548};
549
573struct MOTOR_CONFIG {
574 static constexpr uint16_t ADDRESS = 0x060;
575 union {
576 uint32_t value;
577 struct {
578 uint32_t N_POLE_PAIRS : 7;
579 uint32_t : 9;
580 uint32_t TYPE : 2;
581 uint32_t : 14;
582 } bits;
583 };
584};
585
620struct MOTION_CONFIG {
621 static constexpr uint16_t ADDRESS = 0x061;
622 struct PHI_E {
623 static constexpr uint16_t ADDRESS = 0x063;
624 union {
625 uint32_t value;
626 struct {
627 int16_t PHI_E : 16;
628 uint16_t : 16;
629 } bits;
630 };
631 };
632
650 struct CONFIG {
651 static constexpr uint16_t ADDRESS = 0x080;
652 union {
653 uint32_t value;
654 struct {
655 uint32_t SV_MODE : 2;
656 uint32_t POLARITY : 1;
657 uint32_t CENTER_ALIGNED : 1;
658 uint32_t PWM_FREQ_DIV : 4;
659 uint32_t : 24;
660 } bits;
661 };
662 };
663
678 struct MAXCNT {
679 static constexpr uint16_t ADDRESS = 0x081;
680 union {
681 uint32_t value;
682 struct {
683 uint32_t MAXCNT : 16;
684 uint32_t : 16;
685 } bits;
686 };
687 };
688
702 struct SWITCH_LIMIT {
703 static constexpr uint16_t ADDRESS = 0x083;
704 union {
705 uint32_t value;
706 struct {
707 uint32_t SWITCH_VEL_LIMIT : 16;
709 uint32_t : 16;
710 } bits;
711 };
712 };
713
729 struct ABN_PHI_E_PHI_M {
730 static constexpr uint16_t ADDRESS = 0x0A0;
731 union {
732 uint32_t value;
733 struct {
734 int16_t PHI_E_ABN : 16;
735 int16_t PHI_M_ABN : 16;
736 } bits;
737 };
738 };
739
760 struct ABN_MODE {
761 static constexpr uint16_t ADDRESS = 0x0A1;
762 union {
763 uint32_t value;
764 struct {
765 uint32_t A_POL : 1;
766 uint32_t B_POL : 1;
767 uint32_t N_POL : 1;
768 uint32_t COMBINED_N : 1;
769 uint32_t CLEAR_COUNT_ON_N : 1;
770 uint32_t DISABLE_FILTER : 1;
771 uint32_t : 2;
772 uint32_t CLN : 1;
773 uint32_t : 3;
774 uint32_t DIRECTION : 1;
775 uint32_t : 19;
776 } bits;
777 };
778 };
779
792 struct ABN_CPR {
794 static constexpr uint16_t ADDRESS = (0 << 9) | 0xA2;
795
796 union {
797 uint32_t value;
798 struct {
799 uint32_t CPR : 24;
800 uint32_t : 8;
801 } bits;
802 };
803
808 uint32_t calculateInverseCPR() const {
809 auto cpr = bits.CPR;
810 return cpr ? static_cast<uint32_t>((uint64_t{1} << 32) / cpr) : 0u;
811 }
812 };
813
827 struct ABN_CPR_INV {
828 static constexpr uint16_t ADDRESS = 0x0A3;
829 union {
830 uint32_t value;
831 struct {
832 uint32_t ABN_CPR_INV : 32;
833 } bits;
834 };
835 };
836
850 struct ABN_COUNT {
851 static constexpr uint16_t ADDRESS = 0x0A4;
852 union {
853 uint32_t value;
854 struct {
855 uint32_t ABN_COUNT : 24;
856 uint32_t : 8;
857 } bits;
858 };
859 };
860
874 struct ABN_COUNT_N {
875 static constexpr uint16_t ADDRESS = 0x0A5;
876 union {
877 uint32_t value;
878 struct {
879 uint32_t ABN_COUNT_N : 24;
880 uint32_t : 8;
881 } bits;
882 };
883 };
884
899 struct ABN_PHI_E_OFFSET {
900 static constexpr uint16_t ADDRESS = 0x0A6;
901 union {
902 uint32_t value;
903 struct {
904 int16_t ABN_PHI_E_OFFSET : 16;
905 uint16_t : 16;
906 } bits;
907 };
908 };
909
926 struct HALL_MODE {
927 static constexpr uint16_t ADDRESS = 0x0C0;
928 union {
929 uint32_t value;
930 struct {
931 uint32_t POLARITY : 1;
932 uint32_t EXTRAPOLATION : 1;
933 uint32_t : 2;
934 uint32_t ORDER : 3;
935 uint32_t : 1;
936 uint32_t FILTER : 8;
937 uint32_t : 16;
938 } bits;
939 };
940 };
941
955 struct HALL_DPHI_MAX {
956 static constexpr uint16_t ADDRESS = 0x0C1;
957 union {
958 uint32_t value;
959 struct {
960 uint16_t HALL_DPHI_MAX;
961 uint16_t _reserved;
962 } bits;
963 };
964 };
965
979 struct HALL_PHI_E_OFFSET {
980 static constexpr uint16_t ADDRESS = 0x0C2;
981 union {
982 uint32_t value;
983 struct {
984 int16_t HALL_PHI_E_OFFSET;
985 uint16_t _reserved;
986 } bits;
987 };
988 };
989
1003 struct HALL_COUNT {
1004 static constexpr uint16_t ADDRESS = 0x0C3;
1005 union {
1006 uint32_t value;
1007 struct {
1008 int16_t HALL_COUNT;
1009 uint16_t _reserved;
1010 } bits;
1011 };
1012 };
1013
1029 struct HALL_PHI_E_EXTRAPOLATED_PHI_E {
1030 static constexpr uint16_t ADDRESS = 0x0C4;
1031 union {
1032 uint32_t value;
1033 struct {
1034 int16_t PHI_E_EXTRAPOLATED;
1035 int16_t PHI_E;
1036 } bits;
1037 };
1038 };
1039
1055 struct HALL_POSITION_060_000 {
1056 static constexpr uint16_t ADDRESS = 0x0C5;
1057 union {
1058 uint32_t value;
1059 struct {
1060 int16_t POSITION_060 : 16;
1061 int16_t POSITION_000 : 16;
1062 } bits;
1063 };
1064 static constexpr int16_t RESET_POSITION_060 = 0x2AAA;
1065 static constexpr int16_t RESET_POSITION_000 = 0x0000;
1066 };
1067
1082 struct HALL_POSITION_180_120 {
1083 static constexpr uint16_t ADDRESS = 0x0C6;
1084 union {
1085 uint32_t value;
1086 struct {
1087 int16_t POSITION_180 : 16;
1088 int16_t POSITION_120 : 16;
1089 } bits;
1090 };
1091 static constexpr int16_t RESET_POSITION_180 = 0x8000;
1092 static constexpr int16_t RESET_POSITION_120 = 0x5555;
1093 };
1094
1109 struct HALL_POSITION_300_240 {
1110 static constexpr uint16_t ADDRESS = 0x0C7;
1111 union {
1112 uint32_t value;
1113 struct {
1114 int16_t POSITION_300 : 16;
1115 int16_t POSITION_240 : 16;
1116 } bits;
1117 };
1118 static constexpr int16_t RESET_POSITION_300 = 0xD555;
1119 static constexpr int16_t RESET_POSITION_240 = 0xAAAA;
1120 };
1121
1135 struct BIQUAD_V_A1 {
1136 static constexpr uint16_t ADDRESS = 0x0E0;
1137 int32_t A1 : 24;
1138 int32_t : 8;
1139 static constexpr int32_t RESET_BIQUAD_V_A1 = 0x1C376B;
1140 };
1141
1155 struct BIQUAD_V_A2 {
1156 static constexpr uint16_t ADDRESS = 0x0E1;
1157 int32_t A2 : 24;
1158 int32_t : 8;
1159 static constexpr int32_t RESET_BIQUAD_V_A2 = 0xF38F52;
1160 };
1161
1175 struct BIQUAD_V_B0 {
1176 static constexpr uint16_t ADDRESS = 0x0E2;
1177 int32_t B0 : 24;
1178 int32_t : 8;
1179 static constexpr int32_t RESET_BIQUAD_V_B0 = 0x000E51;
1180 };
1181
1195 struct BIQUAD_V_B1 {
1196 static constexpr uint16_t ADDRESS = 0x0E3;
1197 int32_t B1 : 24;
1198 int32_t : 8;
1199 static constexpr int32_t RESET_BIQUAD_V_B1 = 0x001CA1;
1200 };
1201
1215 struct BIQUAD_V_B2 {
1216 static constexpr uint16_t ADDRESS = 0x0E4;
1217 int32_t B2 : 24;
1218 int32_t : 8;
1219 static constexpr int32_t RESET_BIQUAD_V_B2 = 0x000E51;
1220 };
1221
1235 struct BIQUAD_V_ENABLE {
1236 static constexpr uint16_t ADDRESS = 0x0E5;
1237 union {
1238 uint32_t value;
1239 struct {
1240 uint32_t ENABLED : 1;
1241 uint32_t : 31;
1242 } bits;
1243 };
1244 static constexpr uint32_t RESET_BIQUAD_V_ENABLE = 0x1;
1245 };
1246
1260 struct BIQUAD_T_A1 {
1261 static constexpr uint16_t ADDRESS = 0x0E6;
1262 int32_t A1 : 24;
1263 int32_t : 8;
1264 static constexpr int32_t RESET_BIQUAD_T_A1 = 0x000000;
1265 };
1266
1280 struct BIQUAD_T_A2 {
1281 static constexpr uint16_t ADDRESS = 0x0E7;
1282 int32_t A2 : 24;
1283 int32_t : 8;
1284 static constexpr int32_t RESET_BIQUAD_T_A2 = 0x000000;
1285 };
1286
1300 struct BIQUAD_T_B0 {
1301 static constexpr uint16_t ADDRESS = 0x0E8;
1302 int32_t B0 : 24;
1303 int32_t : 8;
1304 static constexpr int32_t RESET_BIQUAD_T_B0 = 0x100000;
1305 };
1306
1320 struct BIQUAD_T_B1 {
1321 static constexpr uint16_t ADDRESS = 0x0E9;
1322 int32_t B1 : 24;
1323 int32_t : 8;
1324 static constexpr int32_t RESET_BIQUAD_T_B1 = 0x000000;
1325 };
1326
1340 struct BIQUAD_T_B2 {
1341 static constexpr uint16_t ADDRESS = 0x0EA;
1342 int32_t B2 : 24;
1343 int32_t : 8;
1344 static constexpr int32_t RESET_BIQUAD_T_B2 = 0x000000;
1345 };
1346
1360 struct BIQUAD_T_ENABLE {
1361 static constexpr uint16_t ADDRESS = 0x0EB;
1362 union {
1363 uint32_t value;
1364 struct {
1365 uint32_t ENABLE : 1;
1366 uint32_t : 31;
1367 } bits;
1368 };
1369 static constexpr uint32_t RESET_BIQUAD_T_ENABLE = 0x0;
1370 };
1371
1388 struct VELOCITY_CONFIG {
1389 static constexpr uint16_t ADDRESS = 0x100;
1390 union {
1391 uint32_t value;
1392 struct {
1393 uint32_t SELECTION : 8;
1394 uint32_t METER_SYNC_PULSE : 1;
1395 uint32_t METER_TYPE : 2;
1396 uint32_t : 1;
1397 uint32_t MOVING_AVRG_FILTER_SAMPLES : 3;
1398 uint32_t : 17;
1399 } bits;
1400 };
1401 };
1402
1417 struct VELOCITY_SCALING {
1418 static constexpr uint16_t ADDRESS = 0x101;
1419 union {
1420 uint32_t value;
1421 struct {
1422 int16_t VELOCITY_SCALING : 16;
1423 uint16_t : 16;
1424 } bits;
1425 };
1426 static constexpr int16_t RESET_VELOCITY_SCALING =
1427 0x28F6;
1428 };
1429
1447 struct V_MIN_POSDEV_TIME {
1448 static constexpr uint16_t ADDRESS = 0x102;
1449 union {
1450 uint32_t value;
1451 struct {
1452 uint32_t TIME_COUNTER_LIMIT : 16;
1454 uint32_t V_MIN_POS_DEV : 15;
1455 uint32_t : 1;
1456 } bits;
1457 };
1458 static constexpr uint32_t RESET_V_MIN_POS_DEV =
1459 0x001;
1460 static constexpr uint32_t RESET_TIME_COUNTER_LIMIT =
1461 0xFFF0;
1462 };
1463
1477 struct MAX_VEL_DEVIATION {
1478 static constexpr uint16_t ADDRESS = 0x103;
1479 union {
1480 uint32_t value;
1481 struct {
1482 uint32_t MAX_VEL_DEVIATION : 31;
1483 uint32_t : 1;
1484 } bits;
1485 };
1486 static constexpr uint32_t RESET_MAX_VEL_DEVIATION =
1487 0x0010000;
1488 };
1489
1503 struct POSITION_CONFIG {
1504 static constexpr uint16_t ADDRESS = 0x120;
1505 union {
1506 uint32_t value;
1507 struct {
1508 uint8_t SELECTION;
1509 uint8_t : 24;
1510 } bits;
1511 };
1512 };
1513
1527 struct MAX_POS_DEVIATION {
1528 static constexpr uint16_t ADDRESS = 0x121;
1529 union {
1530 uint32_t value;
1531 struct {
1532 uint32_t MAX_POS_ERR : 31;
1533 uint32_t : 1;
1534 } bits;
1535 };
1536 };
1537
1568 struct RAMP_STATUS {
1569 static constexpr uint16_t ADDRESS = 0x140;
1570 union {
1571 uint32_t value;
1572 struct {
1573 uint32_t STATUS_STOP_L : 1;
1574 uint32_t STATUS_STOP_R : 1;
1575 uint32_t STATUS_STOP_H : 1;
1576 uint32_t STATUS_LATCH_L : 1;
1577 uint32_t STATUS_LATCH_R : 1;
1578 uint32_t STATUS_LATCH_H : 1;
1579 uint32_t EVENT_STOP_L : 1;
1580 uint32_t EVENT_STOP_R : 1;
1581 uint32_t EVENT_STOP_H : 1;
1582 uint32_t EVENT_STOP_SG : 1;
1583 uint32_t EVENT_POS_REACHED : 1;
1584 uint32_t VELOCITY_REACHED : 1;
1585 uint32_t POSITION_REACHED : 1;
1586 uint32_t V_ZERO : 1;
1587 uint32_t T_ZEROWAIT_ACTIVE : 1;
1588 uint32_t SECOND_MOVE : 1;
1589 uint32_t STALL_IN_VEL_ERR : 1;
1590 uint32_t STALL_IN_POS_ERR : 1;
1591 uint32_t : 14;
1592 } bits;
1593 };
1594 };
1595
1609 struct RAMP_A1 {
1610 static constexpr uint16_t ADDRESS = 0x141;
1611 uint32_t RAMPER_A1 : 23;
1612 uint32_t : 9;
1613 };
1614
1628 struct RAMP_A2 {
1629 static constexpr uint16_t ADDRESS = 0x142;
1630 uint32_t RAMPER_A2 : 23;
1631 uint32_t : 9;
1632 };
1633
1647 struct RAMP_A_MAX {
1648 static constexpr uint16_t ADDRESS = 0x143;
1649 uint32_t RAMPER_A_MAX : 23;
1650 uint32_t : 9;
1651 };
1652
1666 struct RAMP_D1 {
1667 static constexpr uint16_t ADDRESS = 0x144;
1668 uint32_t RAMPER_D1 : 23;
1669 uint32_t : 9;
1670 };
1671
1685 struct RAMP_D2 {
1686 static constexpr uint16_t ADDRESS = 0x145;
1687 uint32_t RAMPER_D2 : 23;
1688 uint32_t : 9;
1689 };
1690
1704 struct RAMP_D_MAX {
1705 static constexpr uint16_t ADDRESS = 0x146;
1706 uint32_t RAMPER_D_MAX : 23;
1707 uint32_t : 9;
1708 };
1709
1723 struct RAMP_V_START {
1724 static constexpr uint16_t ADDRESS = 0x147;
1725 uint32_t RAMPER_V_START : 23;
1726 uint32_t : 9;
1727 };
1728
1743 struct RAMP_V1 {
1744 static constexpr uint16_t ADDRESS = 0x148;
1745 uint32_t RAMPER_V1 : 27;
1746 uint32_t : 5;
1747 };
1748
1763 struct RAMP_V2 {
1764 static constexpr uint16_t ADDRESS = 0x149;
1765 uint32_t RAMPER_V2 : 27;
1767 uint32_t : 5;
1768 };
1769
1783 struct RAMP_V_STOP {
1784 static constexpr uint16_t ADDRESS = 0x14A;
1785 uint32_t RAMPER_V_STOP : 23;
1786 uint32_t : 9;
1787 };
1788
1802 struct RAMP_V_MAX {
1803 static constexpr uint16_t ADDRESS = 0x14B;
1804 uint32_t RAMPER_V_MAX : 27;
1805 uint32_t : 5;
1806 };
1807
1821 struct RAMP_V_TARGET {
1822 static constexpr uint16_t ADDRESS = 0x14C;
1823 int32_t RAMPER_V_TARGET : 28;
1824 uint32_t : 4;
1825 };
1826
1864 struct RAMP_SWITCH_MODE {
1865 static constexpr uint16_t ADDRESS = 0x14D;
1866 union {
1867 uint32_t value;
1868 struct {
1869 uint32_t STOP_L_ENABLE : 1;
1870 uint32_t STOP_R_ENABLE : 1;
1871 uint32_t STOP_H_ENABLE : 1;
1872 uint32_t STOP_L_POL : 1;
1873 uint32_t STOP_R_POL : 1;
1874 uint32_t STOP_H_POL : 1;
1875 uint32_t SWAP_LR : 1;
1876 uint32_t LATCH_L_ACTIVE : 1;
1877 uint32_t LATCH_L_INACTIVE : 1;
1878 uint32_t LATCH_R_ACTIVE : 1;
1879 uint32_t LATCH_R_INACTIVE : 1;
1880 uint32_t LATCH_H_ACTIVE : 1;
1881 uint32_t LATCH_H_INACTIVE : 1;
1882 uint32_t SG_STOP_ENABLE : 1;
1883 uint32_t SOFTSTOP_ENABLE : 1;
1884 uint32_t SW_HARD_STOP : 1;
1885 uint32_t STOP_ON_POS_DEVIATION : 1;
1886 uint32_t STOP_ON_VEL_DEVIATION : 1;
1887 uint32_t VELOCITY_OVERWRITE : 1;
1888 uint32_t : 13;
1889 } bits;
1890 };
1891 };
1892
1907 struct RAMP_TIME_CONFIG {
1908 static constexpr uint16_t ADDRESS = 0x14E;
1909 union {
1910 uint32_t value;
1911 struct {
1912 uint16_t T_VMAX : 16;
1914 uint16_t T_ZEROWAIT : 16;
1916 } bits;
1917 };
1918 static constexpr uint32_t RESET_T_VMAX = 0x0000;
1919 static constexpr uint32_t RESET_T_ZEROWAIT = 0x0000;
1920 };
1921
1935 struct RAMP_A_ACTUAL {
1936 static constexpr uint16_t ADDRESS = 0x14F;
1937 union {
1938 uint32_t value;
1939 struct {
1940 int32_t A_ACTUAL : 24;
1941 uint32_t : 8;
1942 } bits;
1943 };
1944 static constexpr int32_t RESET_RAMPER_A_ACTUAL =
1945 0x000000;
1946 };
1947
1961 struct RAMP_X_ACTUAL {
1962 static constexpr uint16_t ADDRESS = 0x150;
1963 int32_t X_ACTUAL;
1964 static constexpr int32_t RESET_RAMPER_X_ACTUAL =
1965 0x00000000;
1966 };
1967
1981 struct RAMP_V_ACTUAL {
1982 static constexpr uint16_t ADDRESS = 0x151;
1983 union {
1984 uint32_t value;
1985 struct {
1986 int32_t RAMPER_V_ACTUAL : 28;
1987 uint32_t : 4;
1988 } bits;
1989 };
1990 };
1991
2005 struct RAMP_X_TARGET {
2006 static constexpr uint16_t ADDRESS = 0x152;
2007 int32_t RAMPER_X_TARGET;
2008 };
2009
2024 struct RAMP_PHI_E {
2025 static constexpr uint16_t ADDRESS = 0x153;
2026 union {
2027 uint32_t value;
2028 struct {
2029 int16_t RAMPER_PHI_E;
2030 uint16_t : 16;
2031 } bits;
2032 };
2033 };
2034
2049 struct RAMP_ACC_FF {
2050 static constexpr uint16_t ADDRESS = 0x155;
2051 union {
2052 uint32_t value;
2053 struct {
2054 uint32_t GAIN : 16;
2055 uint32_t SHIFT : 3;
2056 uint32_t : 13;
2057 } bits;
2058 };
2059 };
2060
2074 struct RAMP_X_ACTUAL_LATCH {
2075 static constexpr uint16_t ADDRESS = 0x156;
2076 int32_t RAMPER_X_ACTUAL_LATCH;
2077 };
2078
2093 struct POSITION_ACTUAL_LATCH {
2094 static constexpr uint16_t ADDRESS = 0x157;
2095 int32_t POSITION_ACTUAL_LATCH;
2096 };
2097
2112 struct PRBS_AMPLITUDE {
2113 static constexpr uint16_t ADDRESS = 0x160;
2114 union {
2115 uint32_t value;
2116 struct {
2117 int32_t PRBS_AMPLITUDE : 32;
2118 } bits;
2119 };
2120 static constexpr int32_t RESET_PRBS_AMPLITUDE = 0x00000000;
2121 };
2122
2136 struct PRBS_DOWNSAMPLING_RATIO {
2137 static constexpr uint16_t ADDRESS = 0x161;
2138 union {
2139 uint32_t value;
2140 struct {
2141 uint8_t PRBS_DOWN_SAMPLING_RATIO : 8;
2142 uint32_t : 24;
2143 } bits;
2144 };
2145 static constexpr uint8_t RESET_PRBS_DOWNSAMPLING_RATIO = 0x00;
2146 };
2147
2170 struct PID_CONFIG {
2171 static constexpr uint16_t ADDRESS = 0x180;
2172 union {
2173 uint32_t value;
2174 struct {
2175 uint32_t
2176 KEEP_POS_TARGET : 1;
2177 uint32_t CURRENT_NORM_P : 1;
2178 uint32_t CURRENT_NORM_I : 1;
2179 uint32_t VELOCITY_NORM_P : 2;
2180 uint32_t VELOCITY_NORM_I : 2;
2181 uint32_t POSITION_NORM_P : 2;
2182 uint32_t POSITION_NORM_I : 2;
2183 uint32_t VEL_SCALE : 4;
2184 uint32_t POS_SMPL : 7;
2185 uint32_t VEL_SMPL : 7;
2186 uint32_t : 5;
2187 } bits;
2188 };
2189 static constexpr uint32_t RESET_PID_CONFIG = 0x00000800;
2190 };
2191
2206 struct PID_FLUX_COEFF {
2207 static constexpr uint16_t ADDRESS = 0x181;
2208 union {
2209 uint32_t value;
2210 struct {
2211 int16_t P;
2212 int16_t I;
2213 } bits;
2214 };
2215 };
2216
2231 struct PID_TORQUE_COEFF {
2232 static constexpr uint16_t ADDRESS = 0x182;
2233 union {
2234 uint32_t value;
2235 struct {
2236 int16_t P;
2237 int16_t I;
2238 } bits;
2239 };
2240 };
2241
2256 struct PID_FIELDWEAK_COEFF {
2257 static constexpr uint16_t ADDRESS = 0x183;
2258 union {
2259 uint32_t value;
2260 struct {
2261 int16_t P;
2262 int16_t I;
2263 } bits;
2264 };
2265 };
2266
2280 struct PID_U_S_MAX {
2281 static constexpr uint16_t ADDRESS = 0x184;
2282 uint16_t U_S_MAX;
2283 uint16_t _reserved;
2284 };
2285
2300 struct PID_VELOCITY_COEFF {
2301 static constexpr uint16_t ADDRESS = 0x185;
2302 union {
2303 uint32_t value;
2304 struct {
2305 int16_t P;
2306 int16_t I;
2307 } bits;
2308 };
2309 };
2310
2325 struct PID_POSITION_COEFF {
2326 static constexpr uint16_t ADDRESS = 0x186;
2327 union {
2328 uint32_t value;
2329 struct {
2330 int16_t P;
2331 int16_t I;
2332 } bits;
2333 };
2334 static constexpr int16_t RESET_P = 0x0000;
2335 static constexpr int16_t RESET_I = 0x0000;
2336 };
2337
2352 struct PID_POSITION_TOLERANCE {
2353 static constexpr uint16_t ADDRESS = 0x187;
2354 union {
2355 uint32_t value;
2356 struct {
2357 uint32_t PID_POSITION_TOLERANCE : 31;
2358 uint32_t : 1;
2359 } bits;
2360 };
2361 static constexpr uint32_t RESET_PID_POSITION_TOLERANCE = 0x0000000;
2362 };
2363
2378 struct PID_POSITION_TOLERANCE_DELAY {
2379 static constexpr uint16_t ADDRESS = 0x188;
2380 union {
2381 uint32_t value;
2382 struct {
2383 uint16_t PID_POSITION_TOLERANCE_DELAY;
2384 uint16_t : 16;
2385 } bits;
2386 };
2387 static constexpr uint16_t RESET_PID_POSITION_TOLERANCE_DELAY = 0x0000;
2388 };
2389
2403 struct PID_UQ_UD_LIMITS {
2404 static constexpr uint16_t ADDRESS = 0x189;
2405 union {
2406 uint32_t value;
2407 struct {
2408 uint16_t PID_UQ_UD_LIMITS;
2409 uint16_t : 16;
2410 } bits;
2411 };
2412 static constexpr uint16_t RESET_PID_UQ_UD_LIMITS = 0x5A81;
2413 };
2414
2429 struct PID_TORQUE_FLUX_LIMITS {
2430 static constexpr uint16_t ADDRESS = 0x18A;
2431 union {
2432 uint32_t value;
2433 struct {
2434 uint32_t PID_TORQUE_LIMIT : 15;
2435 uint32_t : 1;
2436 uint32_t PID_FLUX_LIMIT : 15;
2437 uint32_t : 1;
2438 } bits;
2439 };
2440 };
2441
2455 struct PID_VELOCITY_LIMIT {
2456 static constexpr uint16_t ADDRESS = 0x18B;
2457 uint32_t PID_VELOCITY_LIMIT : 31;
2458 uint32_t : 1;
2459 };
2460
2474 struct PID_POSITION_LIMIT_LOW {
2475 static constexpr uint16_t ADDRESS = 0x18C;
2476 int32_t PID_POSITION_LIMIT_LOW;
2477 };
2478
2492 struct PID_POSITION_LIMIT_HIGH {
2493 static constexpr uint16_t ADDRESS = 0x18D;
2494 int32_t PID_POSITION_LIMIT_HIGH;
2495 };
2496
2511 struct PID_TORQUE_FLUX_TARGET {
2512 static constexpr uint16_t ADDRESS = 0x18E;
2513 union {
2514 uint32_t value;
2515 struct {
2516 int16_t PID_TORQUE_TARGET;
2517 int16_t PID_FLUX_TARGET;
2518 } bits;
2519 };
2520 };
2521
2536 struct PID_TORQUE_FLUX_OFFSET {
2537 static constexpr uint16_t ADDRESS = 0x18F;
2538 union {
2539 uint32_t value;
2540 struct {
2541 int16_t PID_TORQUE_OFFSET;
2542 int16_t PID_FLUX_OFFSET;
2543 } bits;
2544 };
2545 };
2546
2560 struct PID_VELOCITY_TARGET {
2561 static constexpr uint16_t ADDRESS = 0x190;
2562 int32_t PID_VELOCITY_TARGET;
2563 };
2564
2578 struct PID_VELOCITY_OFFSET {
2579 static constexpr uint16_t ADDRESS = 0x191;
2580 int32_t PID_VELOCITY_OFFSET;
2581 };
2582
2596 struct PID_POSITION_TARGET {
2597 static constexpr uint16_t ADDRESS = 0x192;
2598 int32_t PID_POSITION_TARGET;
2599 };
2600
2615 struct PID_TORQUE_FLUX_ACTUAL {
2616 static constexpr uint16_t ADDRESS = 0x193;
2617 union {
2618 uint32_t value;
2619 struct {
2620 int16_t PID_TORQUE_ACTUAL;
2621 int16_t PID_FLUX_ACTUAL;
2622 } bits;
2623 };
2624 };
2625
2639 struct PID_VELOCITY_ACTUAL {
2640 static constexpr uint16_t ADDRESS = 0x194;
2641 int32_t PID_VELOCITY_ACTUAL;
2642 };
2643
2657 struct PID_POSITION_ACTUAL {
2658 static constexpr uint16_t ADDRESS = 0x195;
2659 int32_t PID_POSITION_ACTUAL;
2660 };
2661
2675 struct PID_POSITION_ACTUAL_OFFSET {
2676 static constexpr uint16_t ADDRESS = 0x196;
2677 int32_t PID_POSITION_ACTUAL_OFFSET;
2678 };
2679
2693 struct PID_TORQUE_ERROR {
2694 static constexpr uint16_t ADDRESS = 0x197;
2695 int16_t PID_TORQUE_ERROR;
2696 };
2697
2711 struct PID_FLUX_ERROR {
2712 static constexpr uint16_t ADDRESS = 0x198;
2713 int16_t PID_FLUX_ERROR;
2714 };
2715
2729 struct PID_VELOCITY_ERROR {
2730 static constexpr uint16_t ADDRESS = 0x199;
2731 int32_t PID_VELOCITY_ERROR;
2732 };
2733
2747 struct PID_POSITION_ERROR {
2748 static constexpr uint16_t ADDRESS = 0x19A;
2749 int32_t PID_POSITION_ERROR;
2750 };
2751
2765 struct PID_TORQUE_INTEGRATOR {
2766 static constexpr uint16_t ADDRESS = 0x19B;
2767 int32_t PID_TORQUE_INTEGRATOR;
2768 };
2769
2783 struct PID_FLUX_INTEGRATOR {
2784 static constexpr uint16_t ADDRESS = 0x19C;
2785 int32_t PID_FLUX_INTEGRATOR;
2786 };
2787
2801 struct PID_VELOCITY_INTEGRATOR {
2802 static constexpr uint16_t ADDRESS = 0x19D;
2803 int32_t PID_VELOCITY_INTEGRATOR;
2804 };
2805
2819 struct PID_POSITION_INTEGRATOR {
2820 static constexpr uint16_t ADDRESS = 0x19E;
2821 int32_t PID_POSITION_INTEGRATOR;
2822 };
2823
2838 struct PIDIN_TORQUE_FLUX_TARGET {
2839 static constexpr uint16_t ADDRESS = 0x1A0;
2840 union {
2841 uint32_t value;
2842 struct {
2843 int16_t PIDIN_TORQUE_TARGET;
2844 int16_t PIDIN_FLUX_TARGET;
2845 } bits;
2846 };
2847 };
2848
2862 struct PIDIN_VELOCITY_TARGET {
2863 static constexpr uint16_t ADDRESS = 0x1A1;
2864 int32_t PIDIN_VELOCITY_TARGET;
2865 };
2866
2880 struct PIDIN_POSITION_TARGET {
2881 static constexpr uint16_t ADDRESS = 0x1A2;
2882 int32_t PIDIN_POSITION_TARGET;
2883 };
2884
2899 struct PIDIN_TORQUE_FLUX_TARGET_LIMITED {
2900 static constexpr uint16_t ADDRESS = 0x1A3;
2901 union {
2902 uint32_t value;
2903 struct {
2904 int16_t PIDIN_TORQUE_TARGET_LIMITED;
2905 int16_t PIDIN_FLUX_TARGET_LIMITED;
2906 } bits;
2907 };
2908 };
2909
2923 struct PIDIN_VELOCITY_TARGET_LIMITED {
2924 static constexpr uint16_t ADDRESS = 0x1A4;
2925 int32_t PIDIN_VELOCITY_TARGET_LIMITED;
2926 };
2927
2941 struct PIDIN_POSITION_TARGET_LIMITED {
2942 static constexpr uint16_t ADDRESS = 0x1A5;
2943 int32_t PIDIN_POSITION_TARGET_LIMITED;
2944 };
2945
2960 struct FOC_IBETA_IALPHA {
2961 static constexpr uint16_t ADDRESS = 0x1A6;
2962 union {
2963 uint32_t value;
2964 struct {
2965 int16_t IALPHA;
2966 int16_t IBETA;
2967 } bits;
2968 };
2969 };
2970
2985 struct FOC_IQ_ID {
2986 static constexpr uint16_t ADDRESS = 0x1A7;
2987 union {
2988 uint32_t value;
2989 struct {
2990 int16_t ID;
2991 int16_t IQ;
2992 } bits;
2993 };
2994 };
2995
3010 struct FOC_UQ_UD {
3011 static constexpr uint16_t ADDRESS = 0x1A8;
3012 union {
3013 uint32_t value;
3014 struct {
3015 int16_t UD;
3016 int16_t UQ;
3017 } bits;
3018 };
3019 };
3020
3035 struct FOC_UQ_UD_LIMITED {
3036 static constexpr uint16_t ADDRESS = 0x1A9;
3037 union {
3038 uint32_t value;
3039 struct {
3040 int16_t UD;
3041 int16_t UQ;
3042 } bits;
3043 };
3044 };
3045
3060 struct FOC_UBETA_UALPHA {
3061 static constexpr uint16_t ADDRESS = 0x1AA;
3062 union {
3063 uint32_t value;
3064 struct {
3065 int16_t UALPHA;
3066 int16_t UBETA;
3067 } bits;
3068 };
3069 };
3070
3085 struct FOC_UWY_UUX {
3086 static constexpr uint16_t ADDRESS = 0x1AB;
3087 union {
3088 uint32_t value;
3089 struct {
3090 int16_t UUX;
3091 int16_t UWY;
3092 } bits;
3093 };
3094 };
3095
3109 struct FOC_UV {
3110 static constexpr uint16_t ADDRESS = 0x1AC;
3111 int16_t UV;
3112 };
3113
3128 struct PWM_VX2_UX1 {
3129 static constexpr uint16_t ADDRESS = 0x1AD;
3130 union {
3131 uint32_t value;
3132 struct {
3133 uint16_t UX1;
3134 uint16_t VX2;
3135 } bits;
3136 };
3137 };
3138
3153 struct PWM_Y2_WY1 {
3154 static constexpr uint16_t ADDRESS = 0x1AE;
3155 union {
3156 uint32_t value;
3157 struct {
3158 uint16_t WY1;
3159 uint16_t Y2;
3160 } bits;
3161 };
3162 };
3163
3177 struct VELOCITY_FRQ {
3178 static constexpr uint16_t ADDRESS = 0x1AF;
3179 int32_t VELOCITY_FRQ;
3180 };
3181
3195 struct VELOCITY_PER {
3196 static constexpr uint16_t ADDRESS = 0x1B0;
3197 int32_t VELOCITY_PER_VAL;
3198 };
3199
3215 struct U_S_ACTUAL_I_S_ACTUAL {
3216 static constexpr uint16_t ADDRESS = 0x1C0;
3217 union {
3218 uint32_t value;
3219 struct {
3220 uint16_t U_S_ACTUAL;
3221 uint16_t I_S_ACTUAL;
3222 } bits;
3223 };
3224 };
3225
3239 struct P_MOTOR {
3240 static constexpr uint16_t ADDRESS = 0x1C1;
3241 uint32_t P_MECH;
3242 };
3243
3269 struct INPUTS_RAW {
3270 static constexpr uint16_t ADDRESS = 0x1C2;
3271 union {
3272 uint32_t value;
3273 struct {
3274 uint32_t ENC_A : 1;
3275 uint32_t ENC_B : 1;
3276 uint32_t ENC_N : 1;
3277 uint32_t : 5;
3278 uint32_t HALL_U : 1;
3279 uint32_t HALL_V : 1;
3280 uint32_t HALL_W : 1;
3281 uint32_t : 1;
3282 uint32_t REF_SW_R : 1;
3283 uint32_t REF_SW_L : 1;
3284 uint32_t REF_SW_H : 1;
3285 uint32_t ENI : 1;
3286 uint32_t : 4;
3287 uint32_t HALL_U_FILT : 1;
3288 uint32_t HALL_V_FILT : 1;
3289 uint32_t HALL_W_FILT : 1;
3290 uint32_t : 9;
3291 } bits;
3292 };
3293 };
3294
3315 struct OUTPUTS_RAW {
3316 static constexpr uint16_t ADDRESS = 0x1C3;
3317 union {
3318 uint32_t value;
3319 struct {
3320 uint32_t PWM_UX1_L : 1;
3321 uint32_t PWM_UX1_H : 1;
3322 uint32_t PWM_VX2_L : 1;
3323 uint32_t PWM_VX2_H : 1;
3324 uint32_t PWM_WY1_L : 1;
3325 uint32_t PWM_WY1_H : 1;
3326 uint32_t PWM_Y2_L : 1;
3327 uint32_t PWM_Y2_H : 1;
3328 uint32_t : 24;
3329 } bits;
3330 };
3331 };
3332
3366 struct STATUS_FLAGS {
3367 static constexpr uint16_t ADDRESS = 0x1C4;
3368 union {
3369 uint32_t value;
3370 struct {
3371 uint32_t PID_X_TARGET_LIMIT : 1;
3372 uint32_t PID_X_OUTPUT_LIMIT : 1;
3373 uint32_t PID_V_TARGET_LIMIT : 1;
3374 uint32_t PID_V_OUTPUT_LIMIT : 1;
3375 uint32_t PID_ID_TARGET_LIMIT : 1;
3376 uint32_t PID_ID_OUTPUT_LIMIT : 1;
3377 uint32_t PID_IQ_TARGET_LIMIT : 1;
3378 uint32_t PID_IQ_OUTPUT_LIMIT : 1;
3379 uint32_t IPARK_VOLTLIM_LIMIT_U : 1;
3381 uint32_t PWM_SWITCH_LIMIT_ACTIVE : 1;
3382 uint32_t HALL_ERROR : 1;
3383 uint32_t POSITION_TRACKING_ERROR : 1;
3385 uint32_t VELOCITY_TRACKING_ERROR : 1;
3387 uint32_t PID_FW_OUTPUT_LIMIT : 1;
3388 uint32_t : 2;
3389 uint32_t SHORT : 1;
3390 uint32_t : 2;
3391 uint32_t REF_SW_L : 1;
3392 uint32_t REF_SW_R : 1;
3393 uint32_t REF_SW_H : 1;
3394 uint32_t POSITION_REACHED : 1;
3395 uint32_t : 2;
3396 uint32_t ADC_I_CLIPPED : 1;
3397 uint32_t : 1;
3398 uint32_t ENC_N : 1;
3399 uint32_t : 2;
3400 uint32_t ENI : 1;
3401 } bits;
3402 };
3403 };
3404
3419 struct HW_CONFIG {
3420 static constexpr uint16_t ADDRESS = 0x1E3;
3421 enum class BridgeEnable : uint8_t {
3422 Disabled = 0,
3423 Enabled = 1
3424 };
3425 union {
3426 uint32_t value;
3427 struct {
3428 BridgeEnable BRIDGE_ENABLE_U : 1;
3429 BridgeEnable BRIDGE_ENABLE_V : 1;
3430 uint32_t : 30;
3431 } bits;
3432 };
3433 };
3434
3454 struct CFG {
3455 static constexpr uint16_t ADDRESS = 0x1E4;
3456
3458 enum class VsUvloLevel : uint8_t {
3459 VSUVLO_44 = 0,
3460 VSUVLO_46 = 1,
3461 VSUVLO_48 = 2,
3462 VSUVLO_50 = 3,
3463 VSUVLO_52 = 4,
3464 VSUVLO_54 = 5,
3465 VSUVLO_56 = 6,
3466 VSUVLO_58 = 7,
3467 VSUVLO_60 = 8,
3468 VSUVLO_63 = 9,
3469 VSUVLO_66 = 10,
3470 VSUVLO_69 = 11,
3471 VSUVLO_72 = 12,
3472 VSUVLO_75 = 13,
3473 VSUVLO_78 = 14,
3474 VSUVLO_81 = 15
3475 };
3476
3478 enum class GateSourceCurrent : uint8_t {
3479 SOURCE_25MA = 0,
3480 SOURCE_50MA = 1,
3481 SOURCE_80MA = 2,
3482 SOURCE_105MA = 3,
3483 SOURCE_135MA = 4,
3484 SOURCE_160MA = 5,
3485 SOURCE_190MA = 6,
3486 SOURCE_215MA = 7,
3487 SOURCE_290MA = 8,
3488 SOURCE_360MA = 9,
3489 SOURCE_430MA = 10,
3490 SOURCE_500MA = 11,
3491 SOURCE_625MA = 12,
3492 SOURCE_755MA = 13,
3493 SOURCE_885MA = 14,
3494 SOURCE_1000MA = 15
3495 };
3496
3498 enum class GateSinkCurrent : uint8_t {
3499 SINK_50MA = 0,
3500 SINK_100MA = 1,
3501 SINK_160MA = 2,
3502 SINK_210MA = 3,
3503 SINK_270MA = 4,
3504 SINK_320MA = 5,
3505 SINK_380MA = 6,
3506 SINK_430MA = 7,
3507 SINK_580MA = 8,
3508 SINK_720MA = 9,
3509 SINK_860MA = 10,
3510 SINK_1000MA = 11,
3511 SINK_1250MA = 12,
3512 SINK_1510MA = 13,
3513 SINK_1770MA = 14,
3514 SINK_2000MA = 15
3515 };
3516
3517 union {
3518 uint32_t value;
3519 struct {
3520 GateSinkCurrent IGATE_SINK_UVW : 4;
3521 GateSourceCurrent IGATE_SOURCE_UVW : 4;
3522 GateSinkCurrent IGATE_SINK_Y2 : 4;
3523 GateSourceCurrent IGATE_SOURCE_Y2 : 4;
3524 uint32_t ADAPTIVE_MODE_UVW : 1;
3525 uint32_t ADAPTIVE_MODE_Y2 : 1;
3526 uint32_t : 2;
3527 VsUvloLevel VS_UVLO_LVL : 4;
3528 uint32_t : 12;
3529 } bits;
3530 };
3531 };
3532
3549 struct TIMING {
3550 static constexpr uint16_t ADDRESS = 0x1E9;
3551 union {
3552 uint32_t value;
3553 struct {
3554 uint8_t T_DRIVE_SINK_UVW;
3555 uint8_t T_DRIVE_SOURCE_UVW;
3556 uint8_t T_DRIVE_SINK_Y2;
3557 uint8_t T_DRIVE_SOURCE_Y2;
3558 } bits;
3559 };
3560 };
3561
3578 struct BBM {
3579 static constexpr uint16_t ADDRESS = 0x1EA;
3580 union {
3581 uint32_t value;
3582 struct {
3583 uint8_t BBM_L_UVW;
3585 uint8_t BBM_H_UVW;
3586 uint8_t BBM_L_Y2;
3587 uint8_t BBM_H_Y2;
3588 } bits;
3589 };
3590 };
3591
3613 struct PROT {
3614 static constexpr uint16_t ADDRESS = 0x1EB;
3615
3617 enum class TermPwmOnShort : uint8_t {
3618 OFF = 0,
3619 ON = 1
3620 };
3621
3623 enum class RetryCount : uint8_t {
3624 OFF = 0,
3625 ONE = 1,
3626 TWO = 2,
3627 THREE = 3
3628 };
3629
3631 enum class VgsBlanking : uint8_t {
3632 BLK_OFF = 0,
3633 BLK_250NS = 1,
3634 BLK_500NS = 2,
3635 BLK_1000NS = 3
3636 };
3637
3639 enum class VgsDeglitch : uint8_t {
3640 DEG_OFF = 0,
3641 DEG_250NS = 1,
3642 DEG_500NS = 2,
3643 DEG_1000NS = 3,
3644 DEG_2000NS = 4,
3645 DEG_4000NS = 5,
3646 DEG_6000NS = 6,
3647 DEG_8000NS = 7
3648 };
3649
3650 union {
3651 uint32_t value;
3652 struct {
3653 VgsDeglitch VGS_DEGLITCH_UVW : 3;
3654 VgsBlanking VGS_BLANKING_UVW : 2;
3655 uint32_t : 1;
3656 VgsDeglitch VGS_DEGLITCH_Y2 : 3;
3657 VgsBlanking VGS_BLANKING_Y2 : 2;
3658 uint32_t : 2;
3659 RetryCount LS_RETRIES_UVW : 2;
3660 RetryCount HS_RETRIES_UVW : 2;
3661 RetryCount LS_RETRIES_Y2 : 2;
3662 RetryCount HS_RETRIES_Y2 : 2;
3663 uint32_t : 3;
3664 TermPwmOnShort TERM_PWM_ON_SHORT : 1;
3665 uint32_t : 3;
3666 } bits;
3667 };
3668 };
3669
3689 struct OCP_UVW {
3690 static constexpr uint16_t ADDRESS = 0x1EC;
3691
3693 enum class OcpThreshold : uint8_t {
3694 THRES_63MV = 0,
3695 THRES_125MV,
3696 THRES_187MV,
3697 THRES_248MV,
3698 THRES_312MV,
3699 THRES_374MV,
3700 THRES_434MV,
3701 THRES_504MV,
3702 THRES_705MV,
3703 THRES_940MV,
3704 THRES_1180MV,
3705 THRES_1410MV,
3706 THRES_1650MV,
3707 THRES_1880MV,
3708 THRES_2110MV,
3709 THRES_2350MV
3710 };
3711
3713 enum class BlankingTime : uint8_t {
3714 BLK_OFF = 0,
3715 BLK_250NS,
3716 BLK_500NS,
3717 BLK_1000NS,
3718 BLK_2000NS,
3719 BLK_4000NS,
3720 BLK_6000NS,
3721 BLK_8000NS
3722 };
3723
3725 enum class DeglitchTime : uint8_t {
3726 DEG_OFF = 0,
3727 DEG_250NS,
3728 DEG_500NS,
3729 DEG_1000NS,
3730 DEG_2000NS,
3731 DEG_4000NS,
3732 DEG_6000NS,
3733 DEG_8000NS
3734 };
3735
3736 union {
3737 uint32_t value;
3738 struct {
3739 DeglitchTime LS_OCP_DEGLITCH_UVW : 3;
3740 BlankingTime LS_OCP_BLANKING_UVW : 3;
3741 uint32_t : 2;
3742 OcpThreshold LS_OCP_THRES_UVW : 4;
3743 uint32_t : 1;
3744 uint32_t LS_OCP_USE_VDS_UVW : 1;
3745 uint32_t : 1;
3746 DeglitchTime HS_OCP_DEGLITCH_UVW : 3;
3747 BlankingTime HS_OCP_BLANKING_UVW : 3;
3748 uint32_t : 1;
3749 OcpThreshold HS_OCP_THRES_UVW : 4;
3750 uint32_t : 4;
3751 } bits;
3752 };
3753 };
3754
3774 struct OCP_Y2 {
3775 static constexpr uint16_t ADDRESS = 0x1ED;
3776
3778 enum class OcpThreshold : uint8_t {
3779 THRES_63MV = 0,
3780 THRES_125MV,
3781 THRES_187MV,
3782 THRES_248MV,
3783 THRES_312MV,
3784 THRES_374MV,
3785 THRES_434MV,
3786 THRES_504MV,
3787 THRES_705MV,
3788 THRES_940MV,
3789 THRES_1180MV,
3790 THRES_1410MV,
3791 THRES_1650MV,
3792 THRES_1880MV,
3793 THRES_2110MV,
3794 THRES_2350MV
3795 };
3796
3798 enum class BlankingTime : uint8_t {
3799 BLK_OFF = 0,
3800 BLK_250NS,
3801 BLK_500NS,
3802 BLK_1000NS,
3803 BLK_2000NS,
3804 BLK_4000NS,
3805 BLK_6000NS,
3806 BLK_8000NS
3807 };
3808
3810 enum class DeglitchTime : uint8_t {
3811 DEG_OFF = 0,
3812 DEG_250NS,
3813 DEG_500NS,
3814 DEG_1000NS,
3815 DEG_2000NS,
3816 DEG_4000NS,
3817 DEG_6000NS,
3818 DEG_8000NS
3819 };
3820
3821 union {
3822 uint32_t value;
3823 struct {
3824 DeglitchTime LS_OCP_DEGLITCH_Y2 : 3;
3825 BlankingTime LS_OCP_BLANKING_Y2 : 3;
3826 uint32_t : 2;
3827 OcpThreshold LS_OCP_THRES_Y2 : 4;
3828 uint32_t : 1;
3829 uint32_t LS_OCP_USE_VDS_Y2 : 1;
3830 uint32_t : 1;
3831 DeglitchTime HS_OCP_DEGLITCH_Y2 : 3;
3832 BlankingTime HS_OCP_BLANKING_Y2 : 3;
3833 uint32_t : 1;
3834 OcpThreshold HS_OCP_THRES_Y2 : 4;
3835 uint32_t : 4;
3836 } bits;
3837 };
3838 };
3839
3893 struct PROT_ENABLE {
3894 static constexpr uint16_t ADDRESS = 0x1EE;
3895 union {
3896 uint32_t value;
3897 struct {
3898 uint32_t
3899 LS_SHORT_PROT_U : 1;
3900 uint32_t
3901 LS_SHORT_PROT_V : 1;
3902 uint32_t
3903 LS_SHORT_PROT_W : 1;
3904 uint32_t LS_SHORT_PROT_Y2 : 1;
3906 uint32_t LS_VGS_OFF_SHORT_PROT_U : 1;
3908 uint32_t LS_VGS_OFF_SHORT_PROT_V : 1;
3910 uint32_t LS_VGS_OFF_SHORT_PROT_W : 1;
3912 uint32_t LS_VGS_OFF_SHORT_PROT_Y2 : 1;
3914 uint32_t LS_VGS_ON_SHORT_PROT_U : 1;
3916 uint32_t LS_VGS_ON_SHORT_PROT_V : 1;
3918 uint32_t LS_VGS_ON_SHORT_PROT_W : 1;
3920 uint32_t LS_VGS_ON_SHORT_PROT_Y2 : 1;
3922 uint32_t BST_UVLO_PROT_U : 1;
3924 uint32_t BST_UVLO_PROT_V : 1;
3926 uint32_t BST_UVLO_PROT_W : 1;
3928 uint32_t BST_UVLO_PROT_Y2 : 1;
3930 uint32_t
3931 HS_SHORT_PROT_U : 1;
3932 uint32_t
3933 HS_SHORT_PROT_V : 1;
3934 uint32_t
3935 HS_SHORT_PROT_W : 1;
3936 uint32_t HS_SHORT_PROT_Y2 : 1;
3938 uint32_t HS_VGS_OFF_SHORT_PROT_U : 1;
3940 uint32_t HS_VGS_OFF_SHORT_PROT_V : 1;
3942 uint32_t HS_VGS_OFF_SHORT_PROT_W : 1;
3944 uint32_t HS_VGS_OFF_SHORT_PROT_Y2 : 1;
3946 uint32_t HS_VGS_ON_SHORT_PROT_U : 1;
3948 uint32_t HS_VGS_ON_SHORT_PROT_V : 1;
3950 uint32_t HS_VGS_ON_SHORT_PROT_W : 1;
3952 uint32_t HS_VGS_ON_SHORT_PROT_Y2 : 1;
3954 uint32_t VDRV_UVLO_PROT : 1;
3955 uint32_t : 1;
3956 uint32_t VS_UVLO_PROT : 1;
3957 } bits;
3958 };
3959 };
3960
4011 struct STATUS_INT_ENABLE {
4012 static constexpr uint16_t ADDRESS = 0x1EF;
4013 union {
4014 uint32_t value;
4015 struct {
4016 uint32_t LS_SHORT_EN_U : 1;
4017 uint32_t LS_SHORT_EN_V : 1;
4018 uint32_t LS_SHORT_EN_W : 1;
4019 uint32_t LS_SHORT_EN_Y2 : 1;
4020 uint32_t LS_VGS_OFF_SHORT_EN_U : 1;
4022 uint32_t LS_VGS_OFF_SHORT_EN_V : 1;
4024 uint32_t LS_VGS_OFF_SHORT_EN_W : 1;
4026 uint32_t LS_VGS_OFF_SHORT_EN_Y2 : 1;
4028 uint32_t LS_VGS_ON_SHORT_EN_U : 1;
4030 uint32_t LS_VGS_ON_SHORT_EN_V : 1;
4032 uint32_t LS_VGS_ON_SHORT_EN_W : 1;
4034 uint32_t LS_VGS_ON_SHORT_EN_Y2 : 1;
4036 uint32_t
4037 BST_UVLO_EN_U : 1;
4038 uint32_t
4039 BST_UVLO_EN_V : 1;
4040 uint32_t
4041 BST_UVLO_EN_W : 1;
4042 uint32_t
4043 BST_UVLO_EN_Y2 : 1;
4044 uint32_t HS_SHORT_EN_U : 1;
4045 uint32_t HS_SHORT_EN_V : 1;
4046 uint32_t HS_SHORT_EN_W : 1;
4047 uint32_t HS_SHORT_EN_Y2 : 1;
4048 uint32_t HS_VGS_OFF_SHORT_EN_U : 1;
4050 uint32_t HS_VGS_OFF_SHORT_EN_V : 1;
4052 uint32_t HS_VGS_OFF_SHORT_EN_W : 1;
4054 uint32_t HS_VGS_OFF_SHORT_EN_Y2 : 1;
4056 uint32_t HS_VGS_ON_SHORT_EN_U : 1;
4058 uint32_t HS_VGS_ON_SHORT_EN_V : 1;
4060 uint32_t HS_VGS_ON_SHORT_EN_W : 1;
4062 uint32_t HS_VGS_ON_SHORT_EN_Y2 : 1;
4064 uint32_t VDRV_UVLO_EN : 1;
4065 uint32_t VDRV_UVLWRN_EN : 1;
4066 uint32_t VS_UVLO_EN : 1;
4067 } bits;
4068 };
4069 };
4070
4115 struct STATUS {
4116 static constexpr uint16_t ADDRESS = 0x1F0;
4117 union {
4118 uint32_t value;
4119 struct {
4120 uint32_t LS_SHORT_U : 1;
4121 uint32_t LS_SHORT_V : 1;
4122 uint32_t LS_SHORT_W : 1;
4123 uint32_t LS_SHORT_Y2 : 1;
4124 uint32_t LS_VGS_OFF_SHORT_U : 1;
4125 uint32_t LS_VGS_OFF_SHORT_V : 1;
4126 uint32_t LS_VGS_OFF_SHORT_W : 1;
4127 uint32_t LS_VGS_OFF_SHORT_Y2 : 1;
4128 uint32_t LS_VGS_ON_SHORT_U : 1;
4129 uint32_t LS_VGS_ON_SHORT_V : 1;
4130 uint32_t LS_VGS_ON_SHORT_W : 1;
4131 uint32_t LS_VGS_ON_SHORT_Y2 : 1;
4132 uint32_t BST_UVLO_U : 1;
4133 uint32_t BST_UVLO_V : 1;
4134 uint32_t BST_UVLO_W : 1;
4135 uint32_t BST_UVLO_Y2 : 1;
4136 uint32_t HS_SHORT_U : 1;
4137 uint32_t HS_SHORT_V : 1;
4138 uint32_t HS_SHORT_W : 1;
4139 uint32_t HS_SHORT_Y2 : 1;
4140 uint32_t HS_VGS_OFF_SHORT_U : 1;
4141 uint32_t HS_VGS_OFF_SHORT_V : 1;
4142 uint32_t HS_VGS_OFF_SHORT_W : 1;
4143 uint32_t HS_VGS_OFF_SHORT_Y2 : 1;
4144 uint32_t HS_VGS_ON_SHORT_U : 1;
4145 uint32_t HS_VGS_ON_SHORT_V : 1;
4146 uint32_t HS_VGS_ON_SHORT_W : 1;
4147 uint32_t HS_VGS_ON_SHORT_Y2 : 1;
4148 uint32_t VDRV_UVLO : 1;
4149 uint32_t VDRV_UVLWRN : 1;
4150 uint32_t VS_UVLO : 1;
4151 } bits;
4152 };
4153 };
4154
4185 struct FAULT {
4186 static constexpr uint16_t ADDRESS = 0x1F1;
4187 union {
4188 uint32_t value;
4189 struct {
4190 uint32_t LS_FAULT_ACTIVE_U : 1;
4191 uint32_t LS_FAULT_ACTIVE_V : 1;
4192 uint32_t LS_FAULT_ACTIVE_W : 1;
4193 uint32_t LS_FAULT_ACTIVE_Y2 : 1;
4194 uint32_t : 8;
4195 uint32_t BST_UVLO_STS_U : 1;
4196 uint32_t BST_UVLO_STS_V : 1;
4197 uint32_t BST_UVLO_STS_W : 1;
4198 uint32_t BST_UVLO_STS_Y2 : 1;
4199 uint32_t HS_FAULT_ACTIVE_U : 1;
4200 uint32_t HS_FAULT_ACTIVE_V : 1;
4201 uint32_t HS_FAULT_ACTIVE_W : 1;
4202 uint32_t HS_FAULT_ACTIVE_Y2 : 1;
4203 uint32_t : 9;
4204 uint32_t VDRV_UVLO_STS : 1;
4205 uint32_t VDRV_UVLWRN_STS : 1;
4206 uint32_t VS_UVLO_STS : 1;
4207 } bits;
4208 };
4209 };
4210
4225 struct ADC_I1_I0_EXT {
4226 static constexpr uint16_t ADDRESS = 0x200;
4227 union {
4228 uint32_t value;
4229 struct {
4230 int16_t I0 : 16;
4231 int16_t I1 : 16;
4232 } bits;
4233 };
4234 };
4235
4249 struct ADC_I2_EXT {
4250 static constexpr uint16_t ADDRESS = 0x201;
4251 union {
4252 uint32_t value;
4253 struct {
4254 int16_t I2 : 16;
4255 uint16_t : 16;
4256 } bits;
4257 };
4258 };
4259
4274 struct PWM_VX2_UX1_EXT {
4275 static constexpr uint16_t ADDRESS = 0x202;
4276 union {
4277 uint32_t value;
4278 struct {
4279 uint16_t UX1 : 16;
4280 uint16_t VX2 : 16;
4281 } bits;
4282 };
4283 };
4284
4299 struct PWM_Y2_WY1_EXT {
4300 static constexpr uint16_t ADDRESS = 0x203;
4301 union {
4302 uint32_t value;
4303 struct {
4304 uint16_t WY1 : 16;
4305 uint16_t Y2 : 16;
4306 } bits;
4307 };
4308 };
4309
4323 struct PWM_EXT_Y2_ALT {
4324 static constexpr uint16_t ADDRESS = 0x204;
4325 union {
4326 uint32_t value;
4327 struct {
4328 uint16_t Y2_ALT : 16;
4329 uint16_t : 16;
4330 } bits;
4331 };
4332 };
4333
4349 struct VOLTAGE_EXT {
4350 static constexpr uint16_t ADDRESS = 0x205;
4351 union {
4352 uint32_t value;
4353 struct {
4354 int16_t UD;
4355 int16_t UQ;
4356 } bits;
4357 };
4358 };
4359
4374 struct PHI_EXT {
4375 static constexpr uint16_t ADDRESS = 0x206;
4376 union {
4377 uint32_t value;
4378 struct {
4379 int16_t PHI_E_EXT;
4380 int16_t PHI_M_EXT;
4381 } bits;
4382 };
4383 };
4384
4398 struct VELOCITY_EXT {
4399 static constexpr uint16_t ADDRESS = 0x208;
4400 union {
4401 uint32_t value;
4402 struct {
4403 int32_t VELOCITY_EXT;
4404 } bits;
4405 };
4406 };
4407
4408} // namespace MCC
4409} // namespace register_mode
4410} // namespace tmc9660
tmc9660::bootcfg::LDOVoltage::Disabled
@ Disabled
LDO output disabled.
tmc9660
Definition bootloader_config.hpp:9
tmc9660::MemoryBank::CONFIG
@ CONFIG
Configuration memory (runtime reconfiguration)