HF-TMC9660 Driver
Hardware Agnostic C++ Driver for the TMC9660
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tmc9660_mcc.hpp
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1#pragma once
2#include <cstdint>
3
21namespace TMC9660 {
22namespace MCC {
23
37struct CHIP_ID {
38 static constexpr uint16_t ADDRESS = 0x000;
39 union {
40 uint32_t value;
41 struct {
42 uint32_t ID : 32;
43 } bits;
44 };
45};
46
63struct I1_I0_RAW {
64 static constexpr uint16_t ADDRESS = 0x020;
65 union {
66 uint32_t value;
67 struct {
68 int16_t I1 : 16;
69 int16_t I0 : 16;
70 } bits;
71 };
72};
73
89struct I3_I2_RAW {
90 static constexpr uint16_t ADDRESS = 0x021;
91 union {
92 uint32_t value;
93 struct {
94 int16_t I3 : 16;
95 int16_t I2 : 16;
96 } bits;
97 };
98};
99
114struct U1_U0_RAW {
115 static constexpr uint16_t ADDRESS = 0x022;
116 union {
117 uint32_t value;
118 struct {
119 int16_t U1 : 16;
120 int16_t U0 : 16;
121 } bits;
122 };
123};
124
139struct U3_U2_RAW {
140 static constexpr uint16_t ADDRESS = 0x023;
141 union {
142 uint32_t value;
143 struct {
144 int16_t U3 : 16;
145 int16_t U2 : 16;
146 } bits;
147 };
148};
149
165struct TEMP_VM_RAW {
166 static constexpr uint16_t ADDRESS = 0x024;
167 union {
168 uint32_t value;
169 struct {
170 int16_t TEMP : 16;
171 uint16_t VM : 16;
172 } bits;
173 };
174};
175
190struct AIN1_AIN0_RAW {
191 static constexpr uint16_t ADDRESS = 0x025;
192 union {
193 uint32_t value;
194 struct {
195 uint16_t AIN1 : 16;
196 uint16_t AIN0 : 16;
197 } bits;
198 };
199};
200
215struct AIN3_AIN2_RAW {
216 static constexpr uint16_t ADDRESS = 0x026;
217 union {
218 uint32_t value;
219 struct {
220 uint16_t AIN3 : 16;
221 uint16_t AIN2 : 16;
222 } bits;
223 };
224};
225
265struct I_GEN_CONFIG {
266 static constexpr uint16_t ADDRESS = 0x040;
267 union {
268 uint32_t value;
269 struct {
270 uint32_t UX1_SELECT : 2;
271 uint32_t VX2_SELECT : 2;
272 uint32_t WY1_SELECT : 2;
273 uint32_t Y2_SELECT : 2;
274 uint32_t : 1;
275 uint32_t MEASUREMENT_MODE : 3;
276 uint32_t : 3;
277 uint32_t TRIGGER_SELECT : 1;
278 uint32_t : 3;
279 uint32_t TRIGGER_POS : 16;
280 } bits;
281 };
282};
283
298struct I0_CONFIG {
299 static constexpr uint16_t ADDRESS = 0x041;
300 union {
301 uint32_t value;
302 struct {
303 int16_t OFFSET;
304 int16_t SCALE;
305 } bits;
306 };
307};
308
323struct I1_CONFIG {
324 static constexpr uint16_t ADDRESS = 0x042;
325 union {
326 uint32_t value;
327 struct {
328 int16_t OFFSET;
329 int16_t SCALE;
330 } bits;
331 };
332};
333
348struct I2_CONFIG {
349 static constexpr uint16_t ADDRESS = 0x043;
350 union {
351 uint32_t value;
352 struct {
353 int16_t OFFSET;
354 int16_t SCALE;
355 } bits;
356 };
357};
358
373struct I3_CONFIG {
374 static constexpr uint16_t ADDRESS = 0x044;
375 union {
376 uint32_t value;
377 struct {
378 int16_t OFFSET;
379 int16_t SCALE;
380 } bits;
381 };
382};
383
398struct I1_I0_SCALED {
399 static constexpr uint16_t ADDRESS = 0x045;
400 union {
401 uint32_t value;
402 struct {
403 int16_t I1 : 16;
404 int16_t I0 : 16;
405 } bits;
406 };
407};
408
423struct I3_I2_SCALED {
424 static constexpr uint16_t ADDRESS = 0x046;
425 union {
426 uint32_t value;
427 struct {
428 int16_t I3 : 16;
429 int16_t I2 : 16;
430 } bits;
431 };
432};
433
448struct IWY_IUX {
449 static constexpr uint16_t ADDRESS = 0x047;
450 union {
451 uint32_t value;
452 struct {
453 int16_t IWY : 16;
454 int16_t IUX : 16;
455 } bits;
456 };
457};
458
472struct IV_RAW {
473 static constexpr uint16_t ADDRESS = 0x048;
474 union {
475 uint32_t value;
476 struct {
477 int16_t IV : 16;
478 uint16_t : 16;
479 } bits;
480 };
481};
482
524struct STATUS {
525 static constexpr uint16_t ADDRESS = 0x049;
526 union {
527 uint32_t value;
528 struct {
529 uint32_t I0_CLIPPED : 1;
530 uint32_t I1_CLIPPED : 1;
531 uint32_t I2_CLIPPED : 1;
532 uint32_t I3_CLIPPED : 1;
533 uint32_t U0_CLIPPED : 1;
534 uint32_t U1_CLIPPED : 1;
535 uint32_t U2_CLIPPED : 1;
536 uint32_t U3_CLIPPED : 1;
537 uint32_t AIN0_CLIPPED : 1;
538 uint32_t AIN1_CLIPPED : 1;
539 uint32_t AIN2_CLIPPED : 1;
540 uint32_t AIN3_CLIPPED : 1;
541 uint32_t VM_CLIPPED : 1;
542 uint32_t TEMP_CLIPPED : 1;
543 uint32_t : 2;
544 uint32_t I0_DONE : 1;
545 uint32_t I1_DONE : 1;
546 uint32_t I2_DONE : 1;
547 uint32_t I3_DONE : 1;
548 uint32_t U0_DONE : 1;
549 uint32_t U1_DONE : 1;
550 uint32_t U2_DONE : 1;
551 uint32_t U3_DONE : 1;
552 uint32_t AIN0_DONE : 1;
553 uint32_t AIN1_DONE : 1;
554 uint32_t AIN2_DONE : 1;
555 uint32_t AIN3_DONE : 1;
556 uint32_t VM_DONE : 1;
557 uint32_t TEMP_DONE : 1;
558 } bits;
559 };
560};
561
585struct MOTOR_CONFIG {
586 static constexpr uint16_t ADDRESS = 0x060;
587 union {
588 uint32_t value;
589 struct {
590 uint32_t N_POLE_PAIRS : 7;
591 uint32_t : 9;
592 uint32_t TYPE : 2;
593 uint32_t : 14;
594 } bits;
595 };
596};
597
632struct MOTION_CONFIG {
633 static constexpr uint16_t ADDRESS = 0x061;
634 struct PHI_E {
635 static constexpr uint16_t ADDRESS = 0x063;
636 union {
637 uint32_t value;
638 struct {
639 int16_t PHI_E : 16;
640 uint16_t : 16;
641 } bits;
642 };
643 };
644
662 struct CONFIG {
663 static constexpr uint16_t ADDRESS = 0x080;
664 union {
665 uint32_t value;
666 struct {
667 uint32_t SV_MODE : 2;
668 uint32_t POLARITY : 1;
669 uint32_t CENTER_ALIGNED : 1;
670 uint32_t PWM_FREQ_DIV : 4;
671 uint32_t : 24;
672 } bits;
673 };
674 };
675
690 struct MAXCNT {
691 static constexpr uint16_t ADDRESS = 0x081;
692 union {
693 uint32_t value;
694 struct {
695 uint32_t MAXCNT : 16;
696 uint32_t : 16;
697 } bits;
698 };
699 };
700
714 struct SWITCH_LIMIT {
715 static constexpr uint16_t ADDRESS = 0x083;
716 union {
717 uint32_t value;
718 struct {
719 uint32_t SWITCH_VEL_LIMIT : 16;
721 uint32_t : 16;
722 } bits;
723 };
724 };
725
741 struct ABN_PHI_E_PHI_M {
742 static constexpr uint16_t ADDRESS = 0x0A0;
743 union {
744 uint32_t value;
745 struct {
746 int16_t PHI_E_ABN : 16;
747 int16_t PHI_M_ABN : 16;
748 } bits;
749 };
750 };
751
772 struct ABN_MODE {
773 static constexpr uint16_t ADDRESS = 0x0A1;
774 union {
775 uint32_t value;
776 struct {
777 uint32_t A_POL : 1;
778 uint32_t B_POL : 1;
779 uint32_t N_POL : 1;
780 uint32_t COMBINED_N : 1;
781 uint32_t CLEAR_COUNT_ON_N : 1;
782 uint32_t DISABLE_FILTER : 1;
783 uint32_t : 2;
784 uint32_t CLN : 1;
785 uint32_t : 3;
786 uint32_t DIRECTION : 1;
787 uint32_t : 19;
788 } bits;
789 };
790 };
791
804 struct ABN_CPR {
806 static constexpr uint16_t ADDRESS = (0 << 9) | 0xA2;
807
808 union {
809 uint32_t value;
810 struct {
811 uint32_t CPR : 24;
812 uint32_t : 8;
813 } bits;
814 };
815
820 uint32_t calculateInverseCPR() const {
821 auto cpr = bits.CPR;
822 return cpr ? static_cast<uint32_t>((uint64_t{1} << 32) / cpr) : 0u;
823 }
824 };
825
839 struct ABN_CPR_INV {
840 static constexpr uint16_t ADDRESS = 0x0A3;
841 union {
842 uint32_t value;
843 struct {
844 uint32_t ABN_CPR_INV : 32;
845 } bits;
846 };
847 };
848
862 struct ABN_COUNT {
863 static constexpr uint16_t ADDRESS = 0x0A4;
864 union {
865 uint32_t value;
866 struct {
867 uint32_t ABN_COUNT : 24;
868 uint32_t : 8;
869 } bits;
870 };
871 };
872
886 struct ABN_COUNT_N {
887 static constexpr uint16_t ADDRESS = 0x0A5;
888 union {
889 uint32_t value;
890 struct {
891 uint32_t ABN_COUNT_N : 24;
892 uint32_t : 8;
893 } bits;
894 };
895 };
896
911 struct ABN_PHI_E_OFFSET {
912 static constexpr uint16_t ADDRESS = 0x0A6;
913 union {
914 uint32_t value;
915 struct {
916 int16_t ABN_PHI_E_OFFSET : 16;
917 uint16_t : 16;
918 } bits;
919 };
920 };
921
938 struct HALL_MODE {
939 static constexpr uint16_t ADDRESS = 0x0C0;
940 union {
941 uint32_t value;
942 struct {
943 uint32_t POLARITY : 1;
944 uint32_t EXTRAPOLATION : 1;
945 uint32_t : 2;
946 uint32_t ORDER : 3;
947 uint32_t : 1;
948 uint32_t FILTER : 8;
949 uint32_t : 16;
950 } bits;
951 };
952 };
953
967 struct HALL_DPHI_MAX {
968 static constexpr uint16_t ADDRESS = 0x0C1;
969 union {
970 uint32_t value;
971 struct {
972 uint16_t HALL_DPHI_MAX;
973 uint16_t _reserved;
974 } bits;
975 };
976 };
977
991 struct HALL_PHI_E_OFFSET {
992 static constexpr uint16_t ADDRESS = 0x0C2;
993 union {
994 uint32_t value;
995 struct {
996 int16_t HALL_PHI_E_OFFSET;
997 uint16_t _reserved;
998 } bits;
999 };
1000 };
1001
1015 struct HALL_COUNT {
1016 static constexpr uint16_t ADDRESS = 0x0C3;
1017 union {
1018 uint32_t value;
1019 struct {
1020 int16_t HALL_COUNT;
1021 uint16_t _reserved;
1022 } bits;
1023 };
1024 };
1025
1041 struct HALL_PHI_E_EXTRAPOLATED_PHI_E {
1042 static constexpr uint16_t ADDRESS = 0x0C4;
1043 union {
1044 uint32_t value;
1045 struct {
1046 int16_t PHI_E_EXTRAPOLATED;
1047 int16_t PHI_E;
1048 } bits;
1049 };
1050 };
1051
1067 struct HALL_POSITION_060_000 {
1068 static constexpr uint16_t ADDRESS = 0x0C5;
1069 union {
1070 uint32_t value;
1071 struct {
1072 int16_t POSITION_060 : 16;
1073 int16_t POSITION_000 : 16;
1074 } bits;
1075 };
1076 static constexpr int16_t RESET_POSITION_060 = 0x2AAA;
1077 static constexpr int16_t RESET_POSITION_000 = 0x0000;
1078 };
1079
1094 struct HALL_POSITION_180_120 {
1095 static constexpr uint16_t ADDRESS = 0x0C6;
1096 union {
1097 uint32_t value;
1098 struct {
1099 int16_t POSITION_180 : 16;
1100 int16_t POSITION_120 : 16;
1101 } bits;
1102 };
1103 static constexpr int16_t RESET_POSITION_180 = 0x8000;
1104 static constexpr int16_t RESET_POSITION_120 = 0x5555;
1105 };
1106
1121 struct HALL_POSITION_300_240 {
1122 static constexpr uint16_t ADDRESS = 0x0C7;
1123 union {
1124 uint32_t value;
1125 struct {
1126 int16_t POSITION_300 : 16;
1127 int16_t POSITION_240 : 16;
1128 } bits;
1129 };
1130 static constexpr int16_t RESET_POSITION_300 = 0xD555;
1131 static constexpr int16_t RESET_POSITION_240 = 0xAAAA;
1132 };
1133
1147 struct BIQUAD_V_A1 {
1148 static constexpr uint16_t ADDRESS = 0x0E0;
1149 int32_t A1 : 24;
1150 int32_t : 8;
1151 static constexpr int32_t RESET_BIQUAD_V_A1 = 0x1C376B;
1152 };
1153
1167 struct BIQUAD_V_A2 {
1168 static constexpr uint16_t ADDRESS = 0x0E1;
1169 int32_t A2 : 24;
1170 int32_t : 8;
1171 static constexpr int32_t RESET_BIQUAD_V_A2 = 0xF38F52;
1172 };
1173
1187 struct BIQUAD_V_B0 {
1188 static constexpr uint16_t ADDRESS = 0x0E2;
1189 int32_t B0 : 24;
1190 int32_t : 8;
1191 static constexpr int32_t RESET_BIQUAD_V_B0 = 0x000E51;
1192 };
1193
1207 struct BIQUAD_V_B1 {
1208 static constexpr uint16_t ADDRESS = 0x0E3;
1209 int32_t B1 : 24;
1210 int32_t : 8;
1211 static constexpr int32_t RESET_BIQUAD_V_B1 = 0x001CA1;
1212 };
1213
1227 struct BIQUAD_V_B2 {
1228 static constexpr uint16_t ADDRESS = 0x0E4;
1229 int32_t B2 : 24;
1230 int32_t : 8;
1231 static constexpr int32_t RESET_BIQUAD_V_B2 = 0x000E51;
1232 };
1233
1247 struct BIQUAD_V_ENABLE {
1248 static constexpr uint16_t ADDRESS = 0x0E5;
1249 union {
1250 uint32_t value;
1251 struct {
1252 uint32_t ENABLED : 1;
1253 uint32_t : 31;
1254 } bits;
1255 };
1256 static constexpr uint32_t RESET_BIQUAD_V_ENABLE = 0x1;
1257 };
1258
1272 struct BIQUAD_T_A1 {
1273 static constexpr uint16_t ADDRESS = 0x0E6;
1274 int32_t A1 : 24;
1275 int32_t : 8;
1276 static constexpr int32_t RESET_BIQUAD_T_A1 = 0x000000;
1277 };
1278
1292 struct BIQUAD_T_A2 {
1293 static constexpr uint16_t ADDRESS = 0x0E7;
1294 int32_t A2 : 24;
1295 int32_t : 8;
1296 static constexpr int32_t RESET_BIQUAD_T_A2 = 0x000000;
1297 };
1298
1312 struct BIQUAD_T_B0 {
1313 static constexpr uint16_t ADDRESS = 0x0E8;
1314 int32_t B0 : 24;
1315 int32_t : 8;
1316 static constexpr int32_t RESET_BIQUAD_T_B0 = 0x100000;
1317 };
1318
1332 struct BIQUAD_T_B1 {
1333 static constexpr uint16_t ADDRESS = 0x0E9;
1334 int32_t B1 : 24;
1335 int32_t : 8;
1336 static constexpr int32_t RESET_BIQUAD_T_B1 = 0x000000;
1337 };
1338
1352 struct BIQUAD_T_B2 {
1353 static constexpr uint16_t ADDRESS = 0x0EA;
1354 int32_t B2 : 24;
1355 int32_t : 8;
1356 static constexpr int32_t RESET_BIQUAD_T_B2 = 0x000000;
1357 };
1358
1372 struct BIQUAD_T_ENABLE {
1373 static constexpr uint16_t ADDRESS = 0x0EB;
1374 union {
1375 uint32_t value;
1376 struct {
1377 uint32_t ENABLE : 1;
1378 uint32_t : 31;
1379 } bits;
1380 };
1381 static constexpr uint32_t RESET_BIQUAD_T_ENABLE = 0x0;
1382 };
1383
1400 struct VELOCITY_CONFIG {
1401 static constexpr uint16_t ADDRESS = 0x100;
1402 union {
1403 uint32_t value;
1404 struct {
1405 uint32_t SELECTION : 8;
1406 uint32_t METER_SYNC_PULSE : 1;
1407 uint32_t METER_TYPE : 2;
1408 uint32_t : 1;
1409 uint32_t MOVING_AVRG_FILTER_SAMPLES : 3;
1410 uint32_t : 17;
1411 } bits;
1412 };
1413 };
1414
1429 struct VELOCITY_SCALING {
1430 static constexpr uint16_t ADDRESS = 0x101;
1431 union {
1432 uint32_t value;
1433 struct {
1434 int16_t VELOCITY_SCALING : 16;
1435 uint16_t : 16;
1436 } bits;
1437 };
1438 static constexpr int16_t RESET_VELOCITY_SCALING =
1439 0x28F6;
1440 };
1441
1459 struct V_MIN_POSDEV_TIME {
1460 static constexpr uint16_t ADDRESS = 0x102;
1461 union {
1462 uint32_t value;
1463 struct {
1464 uint32_t TIME_COUNTER_LIMIT : 16;
1466 uint32_t V_MIN_POS_DEV : 15;
1467 uint32_t : 1;
1468 } bits;
1469 };
1470 static constexpr uint32_t RESET_V_MIN_POS_DEV =
1471 0x001;
1472 static constexpr uint32_t RESET_TIME_COUNTER_LIMIT =
1473 0xFFF0;
1474 };
1475
1489 struct MAX_VEL_DEVIATION {
1490 static constexpr uint16_t ADDRESS = 0x103;
1491 union {
1492 uint32_t value;
1493 struct {
1494 uint32_t MAX_VEL_DEVIATION : 31;
1495 uint32_t : 1;
1496 } bits;
1497 };
1498 static constexpr uint32_t RESET_MAX_VEL_DEVIATION =
1499 0x0010000;
1500 };
1501
1515 struct POSITION_CONFIG {
1516 static constexpr uint16_t ADDRESS = 0x120;
1517 union {
1518 uint32_t value;
1519 struct {
1520 uint8_t SELECTION;
1521 uint8_t : 24;
1522 } bits;
1523 };
1524 };
1525
1539 struct MAX_POS_DEVIATION {
1540 static constexpr uint16_t ADDRESS = 0x121;
1541 union {
1542 uint32_t value;
1543 struct {
1544 uint32_t MAX_POS_ERR : 31;
1545 uint32_t : 1;
1546 } bits;
1547 };
1548 };
1549
1580 struct RAMP_STATUS {
1581 static constexpr uint16_t ADDRESS = 0x140;
1582 union {
1583 uint32_t value;
1584 struct {
1585 uint32_t STATUS_STOP_L : 1;
1586 uint32_t STATUS_STOP_R : 1;
1587 uint32_t STATUS_STOP_H : 1;
1588 uint32_t STATUS_LATCH_L : 1;
1589 uint32_t STATUS_LATCH_R : 1;
1590 uint32_t STATUS_LATCH_H : 1;
1591 uint32_t EVENT_STOP_L : 1;
1592 uint32_t EVENT_STOP_R : 1;
1593 uint32_t EVENT_STOP_H : 1;
1594 uint32_t EVENT_STOP_SG : 1;
1595 uint32_t EVENT_POS_REACHED : 1;
1596 uint32_t VELOCITY_REACHED : 1;
1597 uint32_t POSITION_REACHED : 1;
1598 uint32_t V_ZERO : 1;
1599 uint32_t T_ZEROWAIT_ACTIVE : 1;
1600 uint32_t SECOND_MOVE : 1;
1601 uint32_t STALL_IN_VEL_ERR : 1;
1602 uint32_t STALL_IN_POS_ERR : 1;
1603 uint32_t : 14;
1604 } bits;
1605 };
1606 };
1607
1621 struct RAMP_A1 {
1622 static constexpr uint16_t ADDRESS = 0x141;
1623 uint32_t RAMPER_A1 : 23;
1624 uint32_t : 9;
1625 };
1626
1640 struct RAMP_A2 {
1641 static constexpr uint16_t ADDRESS = 0x142;
1642 uint32_t RAMPER_A2 : 23;
1643 uint32_t : 9;
1644 };
1645
1659 struct RAMP_A_MAX {
1660 static constexpr uint16_t ADDRESS = 0x143;
1661 uint32_t RAMPER_A_MAX : 23;
1662 uint32_t : 9;
1663 };
1664
1678 struct RAMP_D1 {
1679 static constexpr uint16_t ADDRESS = 0x144;
1680 uint32_t RAMPER_D1 : 23;
1681 uint32_t : 9;
1682 };
1683
1697 struct RAMP_D2 {
1698 static constexpr uint16_t ADDRESS = 0x145;
1699 uint32_t RAMPER_D2 : 23;
1700 uint32_t : 9;
1701 };
1702
1716 struct RAMP_D_MAX {
1717 static constexpr uint16_t ADDRESS = 0x146;
1718 uint32_t RAMPER_D_MAX : 23;
1719 uint32_t : 9;
1720 };
1721
1735 struct RAMP_V_START {
1736 static constexpr uint16_t ADDRESS = 0x147;
1737 uint32_t RAMPER_V_START : 23;
1738 uint32_t : 9;
1739 };
1740
1755 struct RAMP_V1 {
1756 static constexpr uint16_t ADDRESS = 0x148;
1757 uint32_t RAMPER_V1 : 27;
1758 uint32_t : 5;
1759 };
1760
1775 struct RAMP_V2 {
1776 static constexpr uint16_t ADDRESS = 0x149;
1777 uint32_t RAMPER_V2 : 27;
1779 uint32_t : 5;
1780 };
1781
1795 struct RAMP_V_STOP {
1796 static constexpr uint16_t ADDRESS = 0x14A;
1797 uint32_t RAMPER_V_STOP : 23;
1798 uint32_t : 9;
1799 };
1800
1814 struct RAMP_V_MAX {
1815 static constexpr uint16_t ADDRESS = 0x14B;
1816 uint32_t RAMPER_V_MAX : 27;
1817 uint32_t : 5;
1818 };
1819
1833 struct RAMP_V_TARGET {
1834 static constexpr uint16_t ADDRESS = 0x14C;
1835 int32_t RAMPER_V_TARGET : 28;
1836 uint32_t : 4;
1837 };
1838
1876 struct RAMP_SWITCH_MODE {
1877 static constexpr uint16_t ADDRESS = 0x14D;
1878 union {
1879 uint32_t value;
1880 struct {
1881 uint32_t STOP_L_ENABLE : 1;
1882 uint32_t STOP_R_ENABLE : 1;
1883 uint32_t STOP_H_ENABLE : 1;
1884 uint32_t STOP_L_POL : 1;
1885 uint32_t STOP_R_POL : 1;
1886 uint32_t STOP_H_POL : 1;
1887 uint32_t SWAP_LR : 1;
1888 uint32_t LATCH_L_ACTIVE : 1;
1889 uint32_t LATCH_L_INACTIVE : 1;
1890 uint32_t LATCH_R_ACTIVE : 1;
1891 uint32_t LATCH_R_INACTIVE : 1;
1892 uint32_t LATCH_H_ACTIVE : 1;
1893 uint32_t LATCH_H_INACTIVE : 1;
1894 uint32_t SG_STOP_ENABLE : 1;
1895 uint32_t SOFTSTOP_ENABLE : 1;
1896 uint32_t SW_HARD_STOP : 1;
1897 uint32_t STOP_ON_POS_DEVIATION : 1;
1898 uint32_t STOP_ON_VEL_DEVIATION : 1;
1899 uint32_t VELOCITY_OVERWRITE : 1;
1900 uint32_t : 13;
1901 } bits;
1902 };
1903 };
1904
1919 struct RAMP_TIME_CONFIG {
1920 static constexpr uint16_t ADDRESS = 0x14E;
1921 union {
1922 uint32_t value;
1923 struct {
1924 uint16_t T_VMAX : 16;
1926 uint16_t T_ZEROWAIT : 16;
1928 } bits;
1929 };
1930 static constexpr uint32_t RESET_T_VMAX = 0x0000;
1931 static constexpr uint32_t RESET_T_ZEROWAIT = 0x0000;
1932 };
1933
1947 struct RAMP_A_ACTUAL {
1948 static constexpr uint16_t ADDRESS = 0x14F;
1949 union {
1950 uint32_t value;
1951 struct {
1952 int32_t A_ACTUAL : 24;
1953 uint32_t : 8;
1954 } bits;
1955 };
1956 static constexpr int32_t RESET_RAMPER_A_ACTUAL =
1957 0x000000;
1958 };
1959
1973 struct RAMP_X_ACTUAL {
1974 static constexpr uint16_t ADDRESS = 0x150;
1975 int32_t X_ACTUAL;
1976 static constexpr int32_t RESET_RAMPER_X_ACTUAL =
1977 0x00000000;
1978 };
1979
1993 struct RAMP_V_ACTUAL {
1994 static constexpr uint16_t ADDRESS = 0x151;
1995 union {
1996 uint32_t value;
1997 struct {
1998 int32_t RAMPER_V_ACTUAL : 28;
1999 uint32_t : 4;
2000 } bits;
2001 };
2002 };
2003
2017 struct RAMP_X_TARGET {
2018 static constexpr uint16_t ADDRESS = 0x152;
2019 int32_t RAMPER_X_TARGET;
2020 };
2021
2036 struct RAMP_PHI_E {
2037 static constexpr uint16_t ADDRESS = 0x153;
2038 union {
2039 uint32_t value;
2040 struct {
2041 int16_t RAMPER_PHI_E;
2042 uint16_t : 16;
2043 } bits;
2044 };
2045 };
2046
2061 struct RAMP_ACC_FF {
2062 static constexpr uint16_t ADDRESS = 0x155;
2063 union {
2064 uint32_t value;
2065 struct {
2066 uint32_t GAIN : 16;
2067 uint32_t SHIFT : 3;
2068 uint32_t : 13;
2069 } bits;
2070 };
2071 };
2072
2086 struct RAMP_X_ACTUAL_LATCH {
2087 static constexpr uint16_t ADDRESS = 0x156;
2088 int32_t RAMPER_X_ACTUAL_LATCH;
2089 };
2090
2105 struct POSITION_ACTUAL_LATCH {
2106 static constexpr uint16_t ADDRESS = 0x157;
2107 int32_t POSITION_ACTUAL_LATCH;
2108 };
2109
2124 struct PRBS_AMPLITUDE {
2125 static constexpr uint16_t ADDRESS = 0x160;
2126 union {
2127 uint32_t value;
2128 struct {
2129 int32_t PRBS_AMPLITUDE : 32;
2130 } bits;
2131 };
2132 static constexpr int32_t RESET_PRBS_AMPLITUDE = 0x00000000;
2133 };
2134
2148 struct PRBS_DOWNSAMPLING_RATIO {
2149 static constexpr uint16_t ADDRESS = 0x161;
2150 union {
2151 uint32_t value;
2152 struct {
2153 uint8_t PRBS_DOWN_SAMPLING_RATIO : 8;
2154 uint32_t : 24;
2155 } bits;
2156 };
2157 static constexpr uint8_t RESET_PRBS_DOWNSAMPLING_RATIO = 0x00;
2158 };
2159
2182 struct PID_CONFIG {
2183 static constexpr uint16_t ADDRESS = 0x180;
2184 union {
2185 uint32_t value;
2186 struct {
2187 uint32_t
2188 KEEP_POS_TARGET : 1;
2189 uint32_t CURRENT_NORM_P : 1;
2190 uint32_t CURRENT_NORM_I : 1;
2191 uint32_t VELOCITY_NORM_P : 2;
2192 uint32_t VELOCITY_NORM_I : 2;
2193 uint32_t POSITION_NORM_P : 2;
2194 uint32_t POSITION_NORM_I : 2;
2195 uint32_t VEL_SCALE : 4;
2196 uint32_t POS_SMPL : 7;
2197 uint32_t VEL_SMPL : 7;
2198 uint32_t : 5;
2199 } bits;
2200 };
2201 static constexpr uint32_t RESET_PID_CONFIG = 0x00000800;
2202 };
2203
2218 struct PID_FLUX_COEFF {
2219 static constexpr uint16_t ADDRESS = 0x181;
2220 union {
2221 uint32_t value;
2222 struct {
2223 int16_t P;
2224 int16_t I;
2225 } bits;
2226 };
2227 };
2228
2243 struct PID_TORQUE_COEFF {
2244 static constexpr uint16_t ADDRESS = 0x182;
2245 union {
2246 uint32_t value;
2247 struct {
2248 int16_t P;
2249 int16_t I;
2250 } bits;
2251 };
2252 };
2253
2268 struct PID_FIELDWEAK_COEFF {
2269 static constexpr uint16_t ADDRESS = 0x183;
2270 union {
2271 uint32_t value;
2272 struct {
2273 int16_t P;
2274 int16_t I;
2275 } bits;
2276 };
2277 };
2278
2292 struct PID_U_S_MAX {
2293 static constexpr uint16_t ADDRESS = 0x184;
2294 uint16_t U_S_MAX;
2295 uint16_t _reserved;
2296 };
2297
2312 struct PID_VELOCITY_COEFF {
2313 static constexpr uint16_t ADDRESS = 0x185;
2314 union {
2315 uint32_t value;
2316 struct {
2317 int16_t P;
2318 int16_t I;
2319 } bits;
2320 };
2321 };
2322
2337 struct PID_POSITION_COEFF {
2338 static constexpr uint16_t ADDRESS = 0x186;
2339 union {
2340 uint32_t value;
2341 struct {
2342 int16_t P;
2343 int16_t I;
2344 } bits;
2345 };
2346 static constexpr int16_t RESET_P = 0x0000;
2347 static constexpr int16_t RESET_I = 0x0000;
2348 };
2349
2364 struct PID_POSITION_TOLERANCE {
2365 static constexpr uint16_t ADDRESS = 0x187;
2366 union {
2367 uint32_t value;
2368 struct {
2369 uint32_t PID_POSITION_TOLERANCE : 31;
2370 uint32_t : 1;
2371 } bits;
2372 };
2373 static constexpr uint32_t RESET_PID_POSITION_TOLERANCE = 0x0000000;
2374 };
2375
2390 struct PID_POSITION_TOLERANCE_DELAY {
2391 static constexpr uint16_t ADDRESS = 0x188;
2392 union {
2393 uint32_t value;
2394 struct {
2395 uint16_t PID_POSITION_TOLERANCE_DELAY;
2396 uint16_t : 16;
2397 } bits;
2398 };
2399 static constexpr uint16_t RESET_PID_POSITION_TOLERANCE_DELAY = 0x0000;
2400 };
2401
2415 struct PID_UQ_UD_LIMITS {
2416 static constexpr uint16_t ADDRESS = 0x189;
2417 union {
2418 uint32_t value;
2419 struct {
2420 uint16_t PID_UQ_UD_LIMITS;
2421 uint16_t : 16;
2422 } bits;
2423 };
2424 static constexpr uint16_t RESET_PID_UQ_UD_LIMITS = 0x5A81;
2425 };
2426
2441 struct PID_TORQUE_FLUX_LIMITS {
2442 static constexpr uint16_t ADDRESS = 0x18A;
2443 union {
2444 uint32_t value;
2445 struct {
2446 uint32_t PID_TORQUE_LIMIT : 15;
2447 uint32_t : 1;
2448 uint32_t PID_FLUX_LIMIT : 15;
2449 uint32_t : 1;
2450 } bits;
2451 };
2452 };
2453
2467 struct PID_VELOCITY_LIMIT {
2468 static constexpr uint16_t ADDRESS = 0x18B;
2469 uint32_t PID_VELOCITY_LIMIT : 31;
2470 uint32_t : 1;
2471 };
2472
2486 struct PID_POSITION_LIMIT_LOW {
2487 static constexpr uint16_t ADDRESS = 0x18C;
2488 int32_t PID_POSITION_LIMIT_LOW;
2489 };
2490
2504 struct PID_POSITION_LIMIT_HIGH {
2505 static constexpr uint16_t ADDRESS = 0x18D;
2506 int32_t PID_POSITION_LIMIT_HIGH;
2507 };
2508
2523 struct PID_TORQUE_FLUX_TARGET {
2524 static constexpr uint16_t ADDRESS = 0x18E;
2525 union {
2526 uint32_t value;
2527 struct {
2528 int16_t PID_TORQUE_TARGET;
2529 int16_t PID_FLUX_TARGET;
2530 } bits;
2531 };
2532 };
2533
2548 struct PID_TORQUE_FLUX_OFFSET {
2549 static constexpr uint16_t ADDRESS = 0x18F;
2550 union {
2551 uint32_t value;
2552 struct {
2553 int16_t PID_TORQUE_OFFSET;
2554 int16_t PID_FLUX_OFFSET;
2555 } bits;
2556 };
2557 };
2558
2572 struct PID_VELOCITY_TARGET {
2573 static constexpr uint16_t ADDRESS = 0x190;
2574 int32_t PID_VELOCITY_TARGET;
2575 };
2576
2590 struct PID_VELOCITY_OFFSET {
2591 static constexpr uint16_t ADDRESS = 0x191;
2592 int32_t PID_VELOCITY_OFFSET;
2593 };
2594
2608 struct PID_POSITION_TARGET {
2609 static constexpr uint16_t ADDRESS = 0x192;
2610 int32_t PID_POSITION_TARGET;
2611 };
2612
2627 struct PID_TORQUE_FLUX_ACTUAL {
2628 static constexpr uint16_t ADDRESS = 0x193;
2629 union {
2630 uint32_t value;
2631 struct {
2632 int16_t PID_TORQUE_ACTUAL;
2633 int16_t PID_FLUX_ACTUAL;
2634 } bits;
2635 };
2636 };
2637
2651 struct PID_VELOCITY_ACTUAL {
2652 static constexpr uint16_t ADDRESS = 0x194;
2653 int32_t PID_VELOCITY_ACTUAL;
2654 };
2655
2669 struct PID_POSITION_ACTUAL {
2670 static constexpr uint16_t ADDRESS = 0x195;
2671 int32_t PID_POSITION_ACTUAL;
2672 };
2673
2687 struct PID_POSITION_ACTUAL_OFFSET {
2688 static constexpr uint16_t ADDRESS = 0x196;
2689 int32_t PID_POSITION_ACTUAL_OFFSET;
2690 };
2691
2705 struct PID_TORQUE_ERROR {
2706 static constexpr uint16_t ADDRESS = 0x197;
2707 int16_t PID_TORQUE_ERROR;
2708 };
2709
2723 struct PID_FLUX_ERROR {
2724 static constexpr uint16_t ADDRESS = 0x198;
2725 int16_t PID_FLUX_ERROR;
2726 };
2727
2741 struct PID_VELOCITY_ERROR {
2742 static constexpr uint16_t ADDRESS = 0x199;
2743 int32_t PID_VELOCITY_ERROR;
2744 };
2745
2759 struct PID_POSITION_ERROR {
2760 static constexpr uint16_t ADDRESS = 0x19A;
2761 int32_t PID_POSITION_ERROR;
2762 };
2763
2777 struct PID_TORQUE_INTEGRATOR {
2778 static constexpr uint16_t ADDRESS = 0x19B;
2779 int32_t PID_TORQUE_INTEGRATOR;
2780 };
2781
2795 struct PID_FLUX_INTEGRATOR {
2796 static constexpr uint16_t ADDRESS = 0x19C;
2797 int32_t PID_FLUX_INTEGRATOR;
2798 };
2799
2813 struct PID_VELOCITY_INTEGRATOR {
2814 static constexpr uint16_t ADDRESS = 0x19D;
2815 int32_t PID_VELOCITY_INTEGRATOR;
2816 };
2817
2831 struct PID_POSITION_INTEGRATOR {
2832 static constexpr uint16_t ADDRESS = 0x19E;
2833 int32_t PID_POSITION_INTEGRATOR;
2834 };
2835
2850 struct PIDIN_TORQUE_FLUX_TARGET {
2851 static constexpr uint16_t ADDRESS = 0x1A0;
2852 union {
2853 uint32_t value;
2854 struct {
2855 int16_t PIDIN_TORQUE_TARGET;
2856 int16_t PIDIN_FLUX_TARGET;
2857 } bits;
2858 };
2859 };
2860
2874 struct PIDIN_VELOCITY_TARGET {
2875 static constexpr uint16_t ADDRESS = 0x1A1;
2876 int32_t PIDIN_VELOCITY_TARGET;
2877 };
2878
2892 struct PIDIN_POSITION_TARGET {
2893 static constexpr uint16_t ADDRESS = 0x1A2;
2894 int32_t PIDIN_POSITION_TARGET;
2895 };
2896
2911 struct PIDIN_TORQUE_FLUX_TARGET_LIMITED {
2912 static constexpr uint16_t ADDRESS = 0x1A3;
2913 union {
2914 uint32_t value;
2915 struct {
2916 int16_t PIDIN_TORQUE_TARGET_LIMITED;
2917 int16_t PIDIN_FLUX_TARGET_LIMITED;
2918 } bits;
2919 };
2920 };
2921
2935 struct PIDIN_VELOCITY_TARGET_LIMITED {
2936 static constexpr uint16_t ADDRESS = 0x1A4;
2937 int32_t PIDIN_VELOCITY_TARGET_LIMITED;
2938 };
2939
2953 struct PIDIN_POSITION_TARGET_LIMITED {
2954 static constexpr uint16_t ADDRESS = 0x1A5;
2955 int32_t PIDIN_POSITION_TARGET_LIMITED;
2956 };
2957
2972 struct FOC_IBETA_IALPHA {
2973 static constexpr uint16_t ADDRESS = 0x1A6;
2974 union {
2975 uint32_t value;
2976 struct {
2977 int16_t IALPHA;
2978 int16_t IBETA;
2979 } bits;
2980 };
2981 };
2982
2997 struct FOC_IQ_ID {
2998 static constexpr uint16_t ADDRESS = 0x1A7;
2999 union {
3000 uint32_t value;
3001 struct {
3002 int16_t ID;
3003 int16_t IQ;
3004 } bits;
3005 };
3006 };
3007
3022 struct FOC_UQ_UD {
3023 static constexpr uint16_t ADDRESS = 0x1A8;
3024 union {
3025 uint32_t value;
3026 struct {
3027 int16_t UD;
3028 int16_t UQ;
3029 } bits;
3030 };
3031 };
3032
3047 struct FOC_UQ_UD_LIMITED {
3048 static constexpr uint16_t ADDRESS = 0x1A9;
3049 union {
3050 uint32_t value;
3051 struct {
3052 int16_t UD;
3053 int16_t UQ;
3054 } bits;
3055 };
3056 };
3057
3072 struct FOC_UBETA_UALPHA {
3073 static constexpr uint16_t ADDRESS = 0x1AA;
3074 union {
3075 uint32_t value;
3076 struct {
3077 int16_t UALPHA;
3078 int16_t UBETA;
3079 } bits;
3080 };
3081 };
3082
3097 struct FOC_UWY_UUX {
3098 static constexpr uint16_t ADDRESS = 0x1AB;
3099 union {
3100 uint32_t value;
3101 struct {
3102 int16_t UUX;
3103 int16_t UWY;
3104 } bits;
3105 };
3106 };
3107
3121 struct FOC_UV {
3122 static constexpr uint16_t ADDRESS = 0x1AC;
3123 int16_t UV;
3124 };
3125
3140 struct PWM_VX2_UX1 {
3141 static constexpr uint16_t ADDRESS = 0x1AD;
3142 union {
3143 uint32_t value;
3144 struct {
3145 uint16_t UX1;
3146 uint16_t VX2;
3147 } bits;
3148 };
3149 };
3150
3165 struct PWM_Y2_WY1 {
3166 static constexpr uint16_t ADDRESS = 0x1AE;
3167 union {
3168 uint32_t value;
3169 struct {
3170 uint16_t WY1;
3171 uint16_t Y2;
3172 } bits;
3173 };
3174 };
3175
3189 struct VELOCITY_FRQ {
3190 static constexpr uint16_t ADDRESS = 0x1AF;
3191 int32_t VELOCITY_FRQ;
3192 };
3193
3207 struct VELOCITY_PER {
3208 static constexpr uint16_t ADDRESS = 0x1B0;
3209 int32_t VELOCITY_PER_VAL;
3210 };
3211
3227 struct U_S_ACTUAL_I_S_ACTUAL {
3228 static constexpr uint16_t ADDRESS = 0x1C0;
3229 union {
3230 uint32_t value;
3231 struct {
3232 uint16_t U_S_ACTUAL;
3233 uint16_t I_S_ACTUAL;
3234 } bits;
3235 };
3236 };
3237
3251 struct P_MOTOR {
3252 static constexpr uint16_t ADDRESS = 0x1C1;
3253 uint32_t P_MECH;
3254 };
3255
3281 struct INPUTS_RAW {
3282 static constexpr uint16_t ADDRESS = 0x1C2;
3283 union {
3284 uint32_t value;
3285 struct {
3286 uint32_t ENC_A : 1;
3287 uint32_t ENC_B : 1;
3288 uint32_t ENC_N : 1;
3289 uint32_t : 5;
3290 uint32_t HALL_U : 1;
3291 uint32_t HALL_V : 1;
3292 uint32_t HALL_W : 1;
3293 uint32_t : 1;
3294 uint32_t REF_SW_R : 1;
3295 uint32_t REF_SW_L : 1;
3296 uint32_t REF_SW_H : 1;
3297 uint32_t ENI : 1;
3298 uint32_t : 4;
3299 uint32_t HALL_U_FILT : 1;
3300 uint32_t HALL_V_FILT : 1;
3301 uint32_t HALL_W_FILT : 1;
3302 uint32_t : 9;
3303 } bits;
3304 };
3305 };
3306
3327 struct OUTPUTS_RAW {
3328 static constexpr uint16_t ADDRESS = 0x1C3;
3329 union {
3330 uint32_t value;
3331 struct {
3332 uint32_t PWM_UX1_L : 1;
3333 uint32_t PWM_UX1_H : 1;
3334 uint32_t PWM_VX2_L : 1;
3335 uint32_t PWM_VX2_H : 1;
3336 uint32_t PWM_WY1_L : 1;
3337 uint32_t PWM_WY1_H : 1;
3338 uint32_t PWM_Y2_L : 1;
3339 uint32_t PWM_Y2_H : 1;
3340 uint32_t : 24;
3341 } bits;
3342 };
3343 };
3344
3378 struct STATUS_FLAGS {
3379 static constexpr uint16_t ADDRESS = 0x1C4;
3380 union {
3381 uint32_t value;
3382 struct {
3383 uint32_t PID_X_TARGET_LIMIT : 1;
3384 uint32_t PID_X_OUTPUT_LIMIT : 1;
3385 uint32_t PID_V_TARGET_LIMIT : 1;
3386 uint32_t PID_V_OUTPUT_LIMIT : 1;
3387 uint32_t PID_ID_TARGET_LIMIT : 1;
3388 uint32_t PID_ID_OUTPUT_LIMIT : 1;
3389 uint32_t PID_IQ_TARGET_LIMIT : 1;
3390 uint32_t PID_IQ_OUTPUT_LIMIT : 1;
3391 uint32_t IPARK_VOLTLIM_LIMIT_U : 1;
3393 uint32_t PWM_SWITCH_LIMIT_ACTIVE : 1;
3394 uint32_t HALL_ERROR : 1;
3395 uint32_t POSITION_TRACKING_ERROR : 1;
3397 uint32_t VELOCITY_TRACKING_ERROR : 1;
3399 uint32_t PID_FW_OUTPUT_LIMIT : 1;
3400 uint32_t : 2;
3401 uint32_t SHORT : 1;
3402 uint32_t : 2;
3403 uint32_t REF_SW_L : 1;
3404 uint32_t REF_SW_R : 1;
3405 uint32_t REF_SW_H : 1;
3406 uint32_t POSITION_REACHED : 1;
3407 uint32_t : 2;
3408 uint32_t ADC_I_CLIPPED : 1;
3409 uint32_t : 1;
3410 uint32_t ENC_N : 1;
3411 uint32_t : 2;
3412 uint32_t ENI : 1;
3413 } bits;
3414 };
3415 };
3416
3431 struct HW_CONFIG {
3432 static constexpr uint16_t ADDRESS = 0x1E3;
3433 enum class BridgeEnable : uint8_t {
3434 Disabled = 0,
3435 Enabled = 1
3436 };
3437 union {
3438 uint32_t value;
3439 struct {
3440 BridgeEnable BRIDGE_ENABLE_U : 1;
3441 BridgeEnable BRIDGE_ENABLE_V : 1;
3442 uint32_t : 30;
3443 } bits;
3444 };
3445 };
3446
3466 struct CFG {
3467 static constexpr uint16_t ADDRESS = 0x1E4;
3468
3470 enum class VsUvloLevel : uint8_t {
3471 VSUVLO_44 = 0,
3472 VSUVLO_46 = 1,
3473 VSUVLO_48 = 2,
3474 VSUVLO_50 = 3,
3475 VSUVLO_52 = 4,
3476 VSUVLO_54 = 5,
3477 VSUVLO_56 = 6,
3478 VSUVLO_58 = 7,
3479 VSUVLO_60 = 8,
3480 VSUVLO_63 = 9,
3481 VSUVLO_66 = 10,
3482 VSUVLO_69 = 11,
3483 VSUVLO_72 = 12,
3484 VSUVLO_75 = 13,
3485 VSUVLO_78 = 14,
3486 VSUVLO_81 = 15
3487 };
3488
3490 enum class GateSourceCurrent : uint8_t {
3491 SOURCE_25MA = 0,
3492 SOURCE_50MA = 1,
3493 SOURCE_80MA = 2,
3494 SOURCE_105MA = 3,
3495 SOURCE_135MA = 4,
3496 SOURCE_160MA = 5,
3497 SOURCE_190MA = 6,
3498 SOURCE_215MA = 7,
3499 SOURCE_290MA = 8,
3500 SOURCE_360MA = 9,
3501 SOURCE_430MA = 10,
3502 SOURCE_500MA = 11,
3503 SOURCE_625MA = 12,
3504 SOURCE_755MA = 13,
3505 SOURCE_885MA = 14,
3506 SOURCE_1000MA = 15
3507 };
3508
3510 enum class GateSinkCurrent : uint8_t {
3511 SINK_50MA = 0,
3512 SINK_100MA = 1,
3513 SINK_160MA = 2,
3514 SINK_210MA = 3,
3515 SINK_270MA = 4,
3516 SINK_320MA = 5,
3517 SINK_380MA = 6,
3518 SINK_430MA = 7,
3519 SINK_580MA = 8,
3520 SINK_720MA = 9,
3521 SINK_860MA = 10,
3522 SINK_1000MA = 11,
3523 SINK_1250MA = 12,
3524 SINK_1510MA = 13,
3525 SINK_1770MA = 14,
3526 SINK_2000MA = 15
3527 };
3528
3529 union {
3530 uint32_t value;
3531 struct {
3532 GateSinkCurrent IGATE_SINK_UVW : 4;
3533 GateSourceCurrent IGATE_SOURCE_UVW : 4;
3534 GateSinkCurrent IGATE_SINK_Y2 : 4;
3535 GateSourceCurrent IGATE_SOURCE_Y2 : 4;
3536 uint32_t ADAPTIVE_MODE_UVW : 1;
3537 uint32_t ADAPTIVE_MODE_Y2 : 1;
3538 uint32_t : 2;
3539 VsUvloLevel VS_UVLO_LVL : 4;
3540 uint32_t : 12;
3541 } bits;
3542 };
3543 };
3544
3561 struct TIMING {
3562 static constexpr uint16_t ADDRESS = 0x1E9;
3563 union {
3564 uint32_t value;
3565 struct {
3566 uint8_t T_DRIVE_SINK_UVW;
3567 uint8_t T_DRIVE_SOURCE_UVW;
3568 uint8_t T_DRIVE_SINK_Y2;
3569 uint8_t T_DRIVE_SOURCE_Y2;
3570 } bits;
3571 };
3572 };
3573
3590 struct BBM {
3591 static constexpr uint16_t ADDRESS = 0x1EA;
3592 union {
3593 uint32_t value;
3594 struct {
3595 uint8_t BBM_L_UVW;
3597 uint8_t BBM_H_UVW;
3598 uint8_t BBM_L_Y2;
3599 uint8_t BBM_H_Y2;
3600 } bits;
3601 };
3602 };
3603
3625 struct PROT {
3626 static constexpr uint16_t ADDRESS = 0x1EB;
3627
3629 enum class TermPwmOnShort : uint8_t {
3630 OFF = 0,
3631 ON = 1
3632 };
3633
3635 enum class RetryCount : uint8_t {
3636 OFF = 0,
3637 ONE = 1,
3638 TWO = 2,
3639 THREE = 3
3640 };
3641
3643 enum class VgsBlanking : uint8_t {
3644 BLK_OFF = 0,
3645 BLK_250NS = 1,
3646 BLK_500NS = 2,
3647 BLK_1000NS = 3
3648 };
3649
3651 enum class VgsDeglitch : uint8_t {
3652 DEG_OFF = 0,
3653 DEG_250NS = 1,
3654 DEG_500NS = 2,
3655 DEG_1000NS = 3,
3656 DEG_2000NS = 4,
3657 DEG_4000NS = 5,
3658 DEG_6000NS = 6,
3659 DEG_8000NS = 7
3660 };
3661
3662 union {
3663 uint32_t value;
3664 struct {
3665 VgsDeglitch VGS_DEGLITCH_UVW : 3;
3666 VgsBlanking VGS_BLANKING_UVW : 2;
3667 uint32_t : 1;
3668 VgsDeglitch VGS_DEGLITCH_Y2 : 3;
3669 VgsBlanking VGS_BLANKING_Y2 : 2;
3670 uint32_t : 2;
3671 RetryCount LS_RETRIES_UVW : 2;
3672 RetryCount HS_RETRIES_UVW : 2;
3673 RetryCount LS_RETRIES_Y2 : 2;
3674 RetryCount HS_RETRIES_Y2 : 2;
3675 uint32_t : 3;
3676 TermPwmOnShort TERM_PWM_ON_SHORT : 1;
3677 uint32_t : 3;
3678 } bits;
3679 };
3680 };
3681
3701 struct OCP_UVW {
3702 static constexpr uint16_t ADDRESS = 0x1EC;
3703
3705 enum class OcpThreshold : uint8_t {
3706 THRES_63MV = 0,
3707 THRES_125MV,
3708 THRES_187MV,
3709 THRES_248MV,
3710 THRES_312MV,
3711 THRES_374MV,
3712 THRES_434MV,
3713 THRES_504MV,
3714 THRES_705MV,
3715 THRES_940MV,
3716 THRES_1180MV,
3717 THRES_1410MV,
3718 THRES_1650MV,
3719 THRES_1880MV,
3720 THRES_2110MV,
3721 THRES_2350MV
3722 };
3723
3725 enum class BlankingTime : uint8_t {
3726 BLK_OFF = 0,
3727 BLK_250NS,
3728 BLK_500NS,
3729 BLK_1000NS,
3730 BLK_2000NS,
3731 BLK_4000NS,
3732 BLK_6000NS,
3733 BLK_8000NS
3734 };
3735
3737 enum class DeglitchTime : uint8_t {
3738 DEG_OFF = 0,
3739 DEG_250NS,
3740 DEG_500NS,
3741 DEG_1000NS,
3742 DEG_2000NS,
3743 DEG_4000NS,
3744 DEG_6000NS,
3745 DEG_8000NS
3746 };
3747
3748 union {
3749 uint32_t value;
3750 struct {
3751 DeglitchTime LS_OCP_DEGLITCH_UVW : 3;
3752 BlankingTime LS_OCP_BLANKING_UVW : 3;
3753 uint32_t : 2;
3754 OcpThreshold LS_OCP_THRES_UVW : 4;
3755 uint32_t : 1;
3756 uint32_t LS_OCP_USE_VDS_UVW : 1;
3757 uint32_t : 1;
3758 DeglitchTime HS_OCP_DEGLITCH_UVW : 3;
3759 BlankingTime HS_OCP_BLANKING_UVW : 3;
3760 uint32_t : 1;
3761 OcpThreshold HS_OCP_THRES_UVW : 4;
3762 uint32_t : 4;
3763 } bits;
3764 };
3765 };
3766
3786 struct OCP_Y2 {
3787 static constexpr uint16_t ADDRESS = 0x1ED;
3788
3790 enum class OcpThreshold : uint8_t {
3791 THRES_63MV = 0,
3792 THRES_125MV,
3793 THRES_187MV,
3794 THRES_248MV,
3795 THRES_312MV,
3796 THRES_374MV,
3797 THRES_434MV,
3798 THRES_504MV,
3799 THRES_705MV,
3800 THRES_940MV,
3801 THRES_1180MV,
3802 THRES_1410MV,
3803 THRES_1650MV,
3804 THRES_1880MV,
3805 THRES_2110MV,
3806 THRES_2350MV
3807 };
3808
3810 enum class BlankingTime : uint8_t {
3811 BLK_OFF = 0,
3812 BLK_250NS,
3813 BLK_500NS,
3814 BLK_1000NS,
3815 BLK_2000NS,
3816 BLK_4000NS,
3817 BLK_6000NS,
3818 BLK_8000NS
3819 };
3820
3822 enum class DeglitchTime : uint8_t {
3823 DEG_OFF = 0,
3824 DEG_250NS,
3825 DEG_500NS,
3826 DEG_1000NS,
3827 DEG_2000NS,
3828 DEG_4000NS,
3829 DEG_6000NS,
3830 DEG_8000NS
3831 };
3832
3833 union {
3834 uint32_t value;
3835 struct {
3836 DeglitchTime LS_OCP_DEGLITCH_Y2 : 3;
3837 BlankingTime LS_OCP_BLANKING_Y2 : 3;
3838 uint32_t : 2;
3839 OcpThreshold LS_OCP_THRES_Y2 : 4;
3840 uint32_t : 1;
3841 uint32_t LS_OCP_USE_VDS_Y2 : 1;
3842 uint32_t : 1;
3843 DeglitchTime HS_OCP_DEGLITCH_Y2 : 3;
3844 BlankingTime HS_OCP_BLANKING_Y2 : 3;
3845 uint32_t : 1;
3846 OcpThreshold HS_OCP_THRES_Y2 : 4;
3847 uint32_t : 4;
3848 } bits;
3849 };
3850 };
3851
3905 struct PROT_ENABLE {
3906 static constexpr uint16_t ADDRESS = 0x1EE;
3907 union {
3908 uint32_t value;
3909 struct {
3910 uint32_t
3911 LS_SHORT_PROT_U : 1;
3912 uint32_t
3913 LS_SHORT_PROT_V : 1;
3914 uint32_t
3915 LS_SHORT_PROT_W : 1;
3916 uint32_t LS_SHORT_PROT_Y2 : 1;
3918 uint32_t LS_VGS_OFF_SHORT_PROT_U : 1;
3920 uint32_t LS_VGS_OFF_SHORT_PROT_V : 1;
3922 uint32_t LS_VGS_OFF_SHORT_PROT_W : 1;
3924 uint32_t LS_VGS_OFF_SHORT_PROT_Y2 : 1;
3926 uint32_t LS_VGS_ON_SHORT_PROT_U : 1;
3928 uint32_t LS_VGS_ON_SHORT_PROT_V : 1;
3930 uint32_t LS_VGS_ON_SHORT_PROT_W : 1;
3932 uint32_t LS_VGS_ON_SHORT_PROT_Y2 : 1;
3934 uint32_t BST_UVLO_PROT_U : 1;
3936 uint32_t BST_UVLO_PROT_V : 1;
3938 uint32_t BST_UVLO_PROT_W : 1;
3940 uint32_t BST_UVLO_PROT_Y2 : 1;
3942 uint32_t
3943 HS_SHORT_PROT_U : 1;
3944 uint32_t
3945 HS_SHORT_PROT_V : 1;
3946 uint32_t
3947 HS_SHORT_PROT_W : 1;
3948 uint32_t HS_SHORT_PROT_Y2 : 1;
3950 uint32_t HS_VGS_OFF_SHORT_PROT_U : 1;
3952 uint32_t HS_VGS_OFF_SHORT_PROT_V : 1;
3954 uint32_t HS_VGS_OFF_SHORT_PROT_W : 1;
3956 uint32_t HS_VGS_OFF_SHORT_PROT_Y2 : 1;
3958 uint32_t HS_VGS_ON_SHORT_PROT_U : 1;
3960 uint32_t HS_VGS_ON_SHORT_PROT_V : 1;
3962 uint32_t HS_VGS_ON_SHORT_PROT_W : 1;
3964 uint32_t HS_VGS_ON_SHORT_PROT_Y2 : 1;
3966 uint32_t VDRV_UVLO_PROT : 1;
3967 uint32_t : 1;
3968 uint32_t VS_UVLO_PROT : 1;
3969 } bits;
3970 };
3971 };
3972
4023 struct STATUS_INT_ENABLE {
4024 static constexpr uint16_t ADDRESS = 0x1EF;
4025 union {
4026 uint32_t value;
4027 struct {
4028 uint32_t LS_SHORT_EN_U : 1;
4029 uint32_t LS_SHORT_EN_V : 1;
4030 uint32_t LS_SHORT_EN_W : 1;
4031 uint32_t LS_SHORT_EN_Y2 : 1;
4032 uint32_t LS_VGS_OFF_SHORT_EN_U : 1;
4034 uint32_t LS_VGS_OFF_SHORT_EN_V : 1;
4036 uint32_t LS_VGS_OFF_SHORT_EN_W : 1;
4038 uint32_t LS_VGS_OFF_SHORT_EN_Y2 : 1;
4040 uint32_t LS_VGS_ON_SHORT_EN_U : 1;
4042 uint32_t LS_VGS_ON_SHORT_EN_V : 1;
4044 uint32_t LS_VGS_ON_SHORT_EN_W : 1;
4046 uint32_t LS_VGS_ON_SHORT_EN_Y2 : 1;
4048 uint32_t
4049 BST_UVLO_EN_U : 1;
4050 uint32_t
4051 BST_UVLO_EN_V : 1;
4052 uint32_t
4053 BST_UVLO_EN_W : 1;
4054 uint32_t
4055 BST_UVLO_EN_Y2 : 1;
4056 uint32_t HS_SHORT_EN_U : 1;
4057 uint32_t HS_SHORT_EN_V : 1;
4058 uint32_t HS_SHORT_EN_W : 1;
4059 uint32_t HS_SHORT_EN_Y2 : 1;
4060 uint32_t HS_VGS_OFF_SHORT_EN_U : 1;
4062 uint32_t HS_VGS_OFF_SHORT_EN_V : 1;
4064 uint32_t HS_VGS_OFF_SHORT_EN_W : 1;
4066 uint32_t HS_VGS_OFF_SHORT_EN_Y2 : 1;
4068 uint32_t HS_VGS_ON_SHORT_EN_U : 1;
4070 uint32_t HS_VGS_ON_SHORT_EN_V : 1;
4072 uint32_t HS_VGS_ON_SHORT_EN_W : 1;
4074 uint32_t HS_VGS_ON_SHORT_EN_Y2 : 1;
4076 uint32_t VDRV_UVLO_EN : 1;
4077 uint32_t VDRV_UVLWRN_EN : 1;
4078 uint32_t VS_UVLO_EN : 1;
4079 } bits;
4080 };
4081 };
4082
4127 struct STATUS {
4128 static constexpr uint16_t ADDRESS = 0x1F0;
4129 union {
4130 uint32_t value;
4131 struct {
4132 uint32_t LS_SHORT_U : 1;
4133 uint32_t LS_SHORT_V : 1;
4134 uint32_t LS_SHORT_W : 1;
4135 uint32_t LS_SHORT_Y2 : 1;
4136 uint32_t LS_VGS_OFF_SHORT_U : 1;
4137 uint32_t LS_VGS_OFF_SHORT_V : 1;
4138 uint32_t LS_VGS_OFF_SHORT_W : 1;
4139 uint32_t LS_VGS_OFF_SHORT_Y2 : 1;
4140 uint32_t LS_VGS_ON_SHORT_U : 1;
4141 uint32_t LS_VGS_ON_SHORT_V : 1;
4142 uint32_t LS_VGS_ON_SHORT_W : 1;
4143 uint32_t LS_VGS_ON_SHORT_Y2 : 1;
4144 uint32_t BST_UVLO_U : 1;
4145 uint32_t BST_UVLO_V : 1;
4146 uint32_t BST_UVLO_W : 1;
4147 uint32_t BST_UVLO_Y2 : 1;
4148 uint32_t HS_SHORT_U : 1;
4149 uint32_t HS_SHORT_V : 1;
4150 uint32_t HS_SHORT_W : 1;
4151 uint32_t HS_SHORT_Y2 : 1;
4152 uint32_t HS_VGS_OFF_SHORT_U : 1;
4153 uint32_t HS_VGS_OFF_SHORT_V : 1;
4154 uint32_t HS_VGS_OFF_SHORT_W : 1;
4155 uint32_t HS_VGS_OFF_SHORT_Y2 : 1;
4156 uint32_t HS_VGS_ON_SHORT_U : 1;
4157 uint32_t HS_VGS_ON_SHORT_V : 1;
4158 uint32_t HS_VGS_ON_SHORT_W : 1;
4159 uint32_t HS_VGS_ON_SHORT_Y2 : 1;
4160 uint32_t VDRV_UVLO : 1;
4161 uint32_t VDRV_UVLWRN : 1;
4162 uint32_t VS_UVLO : 1;
4163 } bits;
4164 };
4165 };
4166
4197 struct FAULT {
4198 static constexpr uint16_t ADDRESS = 0x1F1;
4199 union {
4200 uint32_t value;
4201 struct {
4202 uint32_t LS_FAULT_ACTIVE_U : 1;
4203 uint32_t LS_FAULT_ACTIVE_V : 1;
4204 uint32_t LS_FAULT_ACTIVE_W : 1;
4205 uint32_t LS_FAULT_ACTIVE_Y2 : 1;
4206 uint32_t : 8;
4207 uint32_t BST_UVLO_STS_U : 1;
4208 uint32_t BST_UVLO_STS_V : 1;
4209 uint32_t BST_UVLO_STS_W : 1;
4210 uint32_t BST_UVLO_STS_Y2 : 1;
4211 uint32_t HS_FAULT_ACTIVE_U : 1;
4212 uint32_t HS_FAULT_ACTIVE_V : 1;
4213 uint32_t HS_FAULT_ACTIVE_W : 1;
4214 uint32_t HS_FAULT_ACTIVE_Y2 : 1;
4215 uint32_t : 9;
4216 uint32_t VDRV_UVLO_STS : 1;
4217 uint32_t VDRV_UVLWRN_STS : 1;
4218 uint32_t VS_UVLO_STS : 1;
4219 } bits;
4220 };
4221 };
4222
4237 struct ADC_I1_I0_EXT {
4238 static constexpr uint16_t ADDRESS = 0x200;
4239 union {
4240 uint32_t value;
4241 struct {
4242 int16_t I0 : 16;
4243 int16_t I1 : 16;
4244 } bits;
4245 };
4246 };
4247
4261 struct ADC_I2_EXT {
4262 static constexpr uint16_t ADDRESS = 0x201;
4263 union {
4264 uint32_t value;
4265 struct {
4266 int16_t I2 : 16;
4267 uint16_t : 16;
4268 } bits;
4269 };
4270 };
4271
4286 struct PWM_VX2_UX1_EXT {
4287 static constexpr uint16_t ADDRESS = 0x202;
4288 union {
4289 uint32_t value;
4290 struct {
4291 uint16_t UX1 : 16;
4292 uint16_t VX2 : 16;
4293 } bits;
4294 };
4295 };
4296
4311 struct PWM_Y2_WY1_EXT {
4312 static constexpr uint16_t ADDRESS = 0x203;
4313 union {
4314 uint32_t value;
4315 struct {
4316 uint16_t WY1 : 16;
4317 uint16_t Y2 : 16;
4318 } bits;
4319 };
4320 };
4321
4335 struct PWM_EXT_Y2_ALT {
4336 static constexpr uint16_t ADDRESS = 0x204;
4337 union {
4338 uint32_t value;
4339 struct {
4340 uint16_t Y2_ALT : 16;
4341 uint16_t : 16;
4342 } bits;
4343 };
4344 };
4345
4361 struct VOLTAGE_EXT {
4362 static constexpr uint16_t ADDRESS = 0x205;
4363 union {
4364 uint32_t value;
4365 struct {
4366 int16_t UD;
4367 int16_t UQ;
4368 } bits;
4369 };
4370 };
4371
4386 struct PHI_EXT {
4387 static constexpr uint16_t ADDRESS = 0x206;
4388 union {
4389 uint32_t value;
4390 struct {
4391 int16_t PHI_E_EXT;
4392 int16_t PHI_M_EXT;
4393 } bits;
4394 };
4395 };
4396
4410 struct VELOCITY_EXT {
4411 static constexpr uint16_t ADDRESS = 0x208;
4412 union {
4413 uint32_t value;
4414 struct {
4415 int32_t VELOCITY_EXT;
4416 } bits;
4417 };
4418 };
4419
4420} // namespace MCC
4421} // namespace TMC9660
TMC9660
Definition tmc9660_adc.hpp:12