tmc9660::register_mode::ADC::SRC_CONFIG Struct Reference

ADC Sources Configuration Register for input routing and multiplexer control. More...

#include <tmc9660_adc.hpp>

Public Types
enum class	Mux2Detour : uint8_t { NO_CHANGE = 0 , DETOUR = 1 }
	MUX detour configuration. More...
enum class	MuxConfig : uint8_t { OFF = 0 , FIRST = 1 , SECOND = 2 , THIRD = 3 }
	MUX configuration options. More...

Public Attributes
union {
uint32_t   value
struct {
Mux2Detour   ADC3_MUX2_DETOUR: 1
uint32_t   : 1
MuxConfig   ADC3_MUX2_CFG: 2
MuxConfig   ADC3_MUX1_CFG: 2
MuxConfig   ADC3_MUX0_CFG: 2
Mux2Detour   ADC2_MUX2_DETOUR: 1
uint32_t   ADC2_MUX3_DIS: 1
MuxConfig   ADC2_MUX2_CFG: 2
MuxConfig   ADC2_MUX1_CFG: 2
MuxConfig   ADC2_MUX0_CFG: 2
Mux2Detour   ADC1_MUX2_DETOUR: 1
uint32_t   : 1
MuxConfig   ADC1_MUX2_CFG: 2
MuxConfig   ADC1_MUX1_CFG: 2
MuxConfig   ADC1_MUX0_CFG: 2
Mux2Detour   ADC0_MUX2_DETOUR: 1
uint32_t   ADC0_MUX3_DIS: 1
MuxConfig   ADC0_MUX2_CFG: 2
MuxConfig   ADC0_MUX1_CFG: 2
MuxConfig   ADC0_MUX0_CFG: 2
}   bits
};

Static Public Attributes
static constexpr uint8_t	ADDRESS = 0x01
	Register address (Block 1)

Detailed Description

ADC Sources Configuration Register for input routing and multiplexer control.

This register configures how internal measurement points are routed to the four ADC multiplexers (ADC0-ADC3). Each ADC can sample up to 4 different inputs in a configurable sequence, with options to skip measurements or repeat specific inputs for improved accuracy.

The register controls measurement timing, input selection, and special modes like detour operations that allow repeating critical measurements for noise reduction or calibration purposes.

Configures the ADC input sources and connections.

Block 1, Address: 0x001

Register Map:

Bits	Name	Access	Description
31	ADC3_MUX2_DETOUR	RW	Skip second MUX2 measurement and repeat MUX1 (AIN3)
measurement. 29:28	ADC3_MUX2_CFG	RW	Measurement position of MUX2 input in
ADC3 sequence. 27:26	ADC3_MUX1_CFG	RW	Measurement position of MUX1 input in
ADC3 sequence. 25:24	ADC3_MUX0_CFG	RW	Measurement position of MUX0 input in
ADC3 sequence. 23	ADC2_MUX2_DETOUR	RW	Skip second MUX2 measurement and repeat
MUX1 (AIN2) measurement. 22	ADC2_MUX3_DIS	RW	Disable measurement of MUX3
input (junction temperature VTJ). 21:20	ADC2_MUX2_CFG	RW	Measurement position
of MUX2 input in ADC2 sequence. 19:18	ADC2_MUX1_CFG	RW	Measurement position
of MUX1 input in ADC2 sequence. 17:16	ADC2_MUX0_CFG	RW	Measurement position
of MUX0 input in ADC2 sequence. 15	ADC1_MUX2_DETOUR	RW	Skip second MUX2

measurement and repeat MUX1 (AIN1) measurement. 13:12 | ADC1_MUX2_CFG | RW | Measurement position of MUX2 input in ADC1 sequence. 11:10 | ADC1_MUX1_CFG | RW | Measurement position of MUX1 input in ADC1 sequence. 9:8 | ADC1_MUX0_CFG | RW | Measurement position of MUX0 input in ADC1 sequence. 7 | ADC0_MUX2_DETOUR | RW | Skip second MUX2 measurement and repeat MUX1 (AIN0) measurement. 6 | ADC0_MUX3_DIS | RW | Disable measurement of MUX3 input (supply voltage). 5:4 | ADC0_MUX2_CFG | RW | Measurement position of MUX2 input in ADC0 sequence. 3:2 | ADC0_MUX1_CFG | RW | Measurement position of MUX1 input in ADC0 sequence. 1:0 | ADC0_MUX0_CFG | RW | Measurement position of MUX0 input in ADC0 sequence.

Note

This register configures the routing of internal measurement points to ADC MUXes.

Member Enumeration Documentation

Mux2Detour

enum class tmc9660::register_mode::ADC::SRC_CONFIG::Mux2Detour : uint8_t

strong

MUX detour configuration.

Enumerator
NO_CHANGE	No changes to the measurement sequence.
DETOUR	Skip MUX2 measurement for a second MUX1 measurement.

MuxConfig

enum class tmc9660::register_mode::ADC::SRC_CONFIG::MuxConfig : uint8_t

strong

MUX configuration options.

Enumerator
OFF	Skip MUX input.
FIRST	Sample MUX input first after trigger.
SECOND	Sample MUX input second after trigger.
THIRD	Sample MUX input third after trigger.

Member Data Documentation

[union]

union { ... } tmc9660::register_mode::ADC::SRC_CONFIG

__pad0__

uint32_t tmc9660::register_mode::ADC::SRC_CONFIG::__pad0__

__pad1__

uint32_t tmc9660::register_mode::ADC::SRC_CONFIG::__pad1__

ADC0_MUX0_CFG

MuxConfig tmc9660::register_mode::ADC::SRC_CONFIG::ADC0_MUX0_CFG

ADC0_MUX1_CFG

MuxConfig tmc9660::register_mode::ADC::SRC_CONFIG::ADC0_MUX1_CFG

ADC0_MUX2_CFG

MuxConfig tmc9660::register_mode::ADC::SRC_CONFIG::ADC0_MUX2_CFG

ADC0_MUX2_DETOUR

Mux2Detour tmc9660::register_mode::ADC::SRC_CONFIG::ADC0_MUX2_DETOUR

ADC0_MUX3_DIS

uint32_t tmc9660::register_mode::ADC::SRC_CONFIG::ADC0_MUX3_DIS

ADC1_MUX0_CFG

MuxConfig tmc9660::register_mode::ADC::SRC_CONFIG::ADC1_MUX0_CFG

ADC1_MUX1_CFG

MuxConfig tmc9660::register_mode::ADC::SRC_CONFIG::ADC1_MUX1_CFG

ADC1_MUX2_CFG

MuxConfig tmc9660::register_mode::ADC::SRC_CONFIG::ADC1_MUX2_CFG

ADC1_MUX2_DETOUR

Mux2Detour tmc9660::register_mode::ADC::SRC_CONFIG::ADC1_MUX2_DETOUR

ADC2_MUX0_CFG

MuxConfig tmc9660::register_mode::ADC::SRC_CONFIG::ADC2_MUX0_CFG

ADC2_MUX1_CFG

MuxConfig tmc9660::register_mode::ADC::SRC_CONFIG::ADC2_MUX1_CFG

ADC2_MUX2_CFG

MuxConfig tmc9660::register_mode::ADC::SRC_CONFIG::ADC2_MUX2_CFG

ADC2_MUX2_DETOUR

Mux2Detour tmc9660::register_mode::ADC::SRC_CONFIG::ADC2_MUX2_DETOUR

ADC2_MUX3_DIS

uint32_t tmc9660::register_mode::ADC::SRC_CONFIG::ADC2_MUX3_DIS

ADC3_MUX0_CFG

MuxConfig tmc9660::register_mode::ADC::SRC_CONFIG::ADC3_MUX0_CFG

ADC3_MUX1_CFG

MuxConfig tmc9660::register_mode::ADC::SRC_CONFIG::ADC3_MUX1_CFG

ADC3_MUX2_CFG

MuxConfig tmc9660::register_mode::ADC::SRC_CONFIG::ADC3_MUX2_CFG

ADC3_MUX2_DETOUR

Mux2Detour tmc9660::register_mode::ADC::SRC_CONFIG::ADC3_MUX2_DETOUR

ADDRESS

constexpr uint8_t tmc9660::register_mode::ADC::SRC_CONFIG::ADDRESS = 0x01

staticconstexpr

Register address (Block 1)

[struct]

struct { ... } tmc9660::register_mode::ADC::SRC_CONFIG::bits

value

uint32_t tmc9660::register_mode::ADC::SRC_CONFIG::value

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The documentation for this struct was generated from the following file:

• tmc9660_adc.hpp