tmc9660_adc.hpp

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#pragma once
#include <cstdint>
 
namespace tmc9660 {
namespace register_mode {
namespace ADC {
 
struct SRC_CONFIG {
  static constexpr uint8_t ADDRESS = 0x01; 
 
  enum class Mux2Detour : uint8_t {
    NO_CHANGE = 0, 
    DETOUR = 1     
  };
 
  enum class MuxConfig : uint8_t {
    OFF = 0,    
    FIRST = 1,  
    SECOND = 2, 
    THIRD = 3   
  };
 
  union {
    uint32_t value;
    struct {
      // ADC3
      Mux2Detour ADC3_MUX2_DETOUR : 1;
      uint32_t : 1;
      MuxConfig ADC3_MUX2_CFG : 2;
      MuxConfig ADC3_MUX1_CFG : 2;
      MuxConfig ADC3_MUX0_CFG : 2;
      // ADC2
      Mux2Detour ADC2_MUX2_DETOUR : 1;
      uint32_t ADC2_MUX3_DIS : 1;
      MuxConfig ADC2_MUX2_CFG : 2;
      MuxConfig ADC2_MUX1_CFG : 2;
      MuxConfig ADC2_MUX0_CFG : 2;
      // ADC1
      Mux2Detour ADC1_MUX2_DETOUR : 1;
      uint32_t : 1;
      MuxConfig ADC1_MUX2_CFG : 2;
      MuxConfig ADC1_MUX1_CFG : 2;
      MuxConfig ADC1_MUX0_CFG : 2;
      // ADC0
      Mux2Detour ADC0_MUX2_DETOUR : 1;
      uint32_t ADC0_MUX3_DIS : 1;
      MuxConfig ADC0_MUX2_CFG : 2;
      MuxConfig ADC0_MUX1_CFG : 2;
      MuxConfig ADC0_MUX0_CFG : 2;
    } bits;
  };
};
 
struct SETUP {
  static constexpr uint8_t ADDRESS = 0x02; 
 
  enum class ADCShiftSample : uint8_t {
    SHIFT_500NS = 0,   
    SHIFT_600NS = 1,   
    SHIFT_700NS = 2,   
    SHIFT_800NS = 3,   
    SHIFT_900NS = 4,   
    SHIFT_1000NS = 5,  
    SHIFT_1100NS = 6,  
    SHIFT_1200NS = 7,  
    SHIFT_1300NS = 8,  
    SHIFT_1400NS = 9,  
    SHIFT_1500NS = 10, 
    SHIFT_1600NS = 11, 
    SHIFT_1700NS = 12, 
    SHIFT_1800NS = 13, 
    SHIFT_1900NS = 14, 
    SHIFT_2000NS = 15  
  };
 
  union {
    uint32_t value;
    struct {
      uint32_t : 16;
      ADCShiftSample ADC_SHIFT_SAMPLE : 4; 
      uint32_t : 12;
    } bits;
  };
};
 
struct STATUS_FLAGS {
  static constexpr uint8_t ADDRESS = 0x05; 
 
  union {
    uint32_t value;
    struct {
      uint32_t RDY_ADC_0 : 1; 
      uint32_t RDY_ADC_1 : 1; 
      uint32_t RDY_ADC_2 : 1; 
      uint32_t RDY_ADC_3 : 1; 
      uint32_t : 4;
      uint32_t ADC0_WTCHDG_FAIL : 1; 
      uint32_t ADC1_WTCHDG_FAIL : 1; 
      uint32_t ADC2_WTCHDG_FAIL : 1; 
      uint32_t ADC3_WTCHDG_FAIL : 1; 
      uint32_t ADC0_MUXSEQ_FAIL : 1; 
      uint32_t ADC1_MUXSEQ_FAIL : 1; 
      uint32_t ADC2_MUXSEQ_FAIL : 1; 
      uint32_t ADC3_MUXSEQ_FAIL : 1; 
      uint32_t : 16;
    } bits;
  };
};
 
struct CSA_SETUP {
  static constexpr uint8_t ADDRESS = 0x07; 
 
  enum class CSAFilterLength : uint8_t {
    OFF = 0,      
    LENGTH_2 = 1, 
    LENGTH_4 = 2, 
    LENGTH_8 = 3  
  };
 
  enum class CSAFilterBW : uint8_t {
    BW_0U55 = 0, 
    BW_0U75 = 1, 
    BW_1U00 = 2, 
    BW_1U35 = 3  
  };
 
  enum class CSAGain : uint8_t {
    X5 = 0,  
    X10 = 1, 
    X20 = 2, 
    X40 = 3  
  };
 
  union {
    uint32_t value;
    struct {
      uint32_t CSA0_EN : 1;       
      uint32_t CSA1_EN : 1;       
      uint32_t CSA2_EN : 1;       
      uint32_t CSA3_EN : 1;       
      CSAGain CSA012_GAIN : 2;    
      uint32_t CSA012_BYPASS : 1; 
      uint32_t : 1;
      CSAGain CSA3_GAIN : 2;    
      uint32_t CSA3_BYPASS : 1; 
      uint32_t : 1;
      CSAFilterBW CSA012_FILT : 2; 
      CSAFilterBW CSA3_FILT : 2;   
      uint32_t : 0;
      CSAFilterLength CSA_AZ_FLTLNGTH_EXP : 4; 
      uint32_t : 12;
    } bits;
  };
};
 
} // namespace ADC
} // namespace register_mode
} // namespace tmc9660