Fault Interrupt Enable Mask Register (FAULT_R_ENA_F) More...

#include <tmc9660_sys_ctrl.hpp>

Public Attributes
union {

uint32_t value

struct {

uint32_t BCK_UVLO_ENA_F: 1
	[0] BUCK_UVLO mask bit for fault pin (reset 1) More...

uint32_t BCK_SHORT_ENA_F: 1
	[1] BUCK_SHORT mask bit for fault pin (reset 1) More...

uint32_t LDOEXT_TSD_ENA_F: 1
	[2] LDOEXT_LTC thermal shutdown mask bit (reset 0) More...

uint32_t LDOEXT1_SHORT_ENA_F: 1
	[3] LDO1EXT_SHORT_LTC mask bit (reset 0) More...

uint32_t LDOEXT2_SHORT_ENA_F: 1
	[4] LDO2EXT_SHORT_LTC mask bit (reset 0) More...

uint32_t CHGP_OK_ENA_F: 1
	[5] CHGP_OK_LTC mask bit (reset 0) More...

uint32_t CHGP_SHORT_ENA_F: 1
	[6] CHGP_SHORT_LTC mask bit (reset 0) More...

uint32_t VSA_UVLO_ENA_F: 1
	[7] VSA_UVLO_LTC mask bit (reset 1) More...

uint32_t VDD_UVLO_ENA_F: 1
	[8] VDD_UVLO_LTC mask bit (reset 1) More...

uint32_t VDDA_UVLO_ENA_F: 1
	[9] VDDA_UVLO_LTC mask bit (reset 1) More...

uint32_t VCCIO_UVLO_ENA_F: 1
	[10] VCCIO_UVLO_LTC mask bit (reset 1) More...

uint32_t LDO1_READY_ENA_F: 1
	[11] LDO1_READY_LTC mask bit (reset 0) More...

uint32_t LDO2_READY_ENA_F: 1
	[12] LDO2_READY_LTC mask bit (reset 0) More...

uint32_t : 19
	[13:31] Reserved More...

} bits

};

Static Public Attributes
static constexpr uint8_t	ADDRESS = 0x00A
	Register address (Block 2)

Detailed Description

Fault Interrupt Enable Mask Register (FAULT_R_ENA_F)

Block 2, Address: 0x00A

Mask register for FAULT_STATUS_LATCHED (FAULT_R_INT). If a bit in this register is set and the corresponding latched fault flag is set, the FAULTN pin will be asserted. Each bit enables or disables the fault pin response for the corresponding latched fault. Default reset values are shown below.

Register Map:

Bits	Name	Access	Reset	Description
12	LDO2_READY_ENA_F	RW	0x0	LDO2_READY_LTC mask bit for fault pin.
11	LDO1_READY_ENA_F	RW	0x0	LDO1_READY_LTC mask bit for fault pin.
10	VCCIO_UVLO_ENA_F	RW	0x1	VCCIO_UVLO_LTC mask bit for fault pin.
9	VDDA_UVLO_ENA_F	RW	0x1	VDDA_UVLO_LTC mask bit for fault pin.
8	VDD_UVLO_ENA_F	RW	0x1	VDD_UVLO_LTC mask bit for fault pin.
7	VSA_UVLO_ENA_F	RW	0x1	VSA_UVLO_LTC mask bit for fault pin.
6	CHGP_SHORT_ENA_F	RW	0x0	CHGP_SHORT_LTC mask bit for fault pin.
5	CHGP_OK_ENA_F	RW	0x0	CHGP_OK_LTC mask bit for fault pin.
4	LDOEXT2_SHORT_ENA_F	RW	0x0	LDO2EXT_SHORT_LTC mask bit for fault pin.
3	LDOEXT1_SHORT_ENA_F	RW	0x0	LDO1EXT_SHORT_LTC mask bit for fault pin.
2	LDOEXT_TSD_ENA_F	RW	0x0	LDOEXT_LTC thermal shutdown mask bit for
fault pin. 1	BCK_SHORT_ENA_F	RW	0x1	BUCK_SHORT mask bit for fault pin.
0	BCK_UVLO_ENA_F	RW	0x1	BUCK_UVLO mask bit for fault pin.

Note: Setting a bit to 1 enables the FAULTN pin assertion for the corresponding latched fault.

Member Data Documentation

◆ [union]

union { ... } TMC9660::SYS_CTRL::FAULT_INT_ENABLE

◆ pad0

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::__pad0__

[13:31] Reserved

◆ ADDRESS

constexpr uint8_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::ADDRESS = 0x00A

staticconstexpr

Register address (Block 2)

◆ BCK_SHORT_ENA_F

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::BCK_SHORT_ENA_F

[1] BUCK_SHORT mask bit for fault pin (reset 1)

◆ BCK_UVLO_ENA_F

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::BCK_UVLO_ENA_F

[0] BUCK_UVLO mask bit for fault pin (reset 1)

◆ [struct]

struct { ... } TMC9660::SYS_CTRL::FAULT_INT_ENABLE::bits

◆ CHGP_OK_ENA_F

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::CHGP_OK_ENA_F

[5] CHGP_OK_LTC mask bit (reset 0)

◆ CHGP_SHORT_ENA_F

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::CHGP_SHORT_ENA_F

[6] CHGP_SHORT_LTC mask bit (reset 0)

◆ LDO1_READY_ENA_F

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::LDO1_READY_ENA_F

[11] LDO1_READY_LTC mask bit (reset 0)

◆ LDO2_READY_ENA_F

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::LDO2_READY_ENA_F

[12] LDO2_READY_LTC mask bit (reset 0)

◆ LDOEXT1_SHORT_ENA_F

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::LDOEXT1_SHORT_ENA_F

[3] LDO1EXT_SHORT_LTC mask bit (reset 0)

◆ LDOEXT2_SHORT_ENA_F

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::LDOEXT2_SHORT_ENA_F

[4] LDO2EXT_SHORT_LTC mask bit (reset 0)

◆ LDOEXT_TSD_ENA_F

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::LDOEXT_TSD_ENA_F

[2] LDOEXT_LTC thermal shutdown mask bit (reset 0)

◆ value

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::value

◆ VCCIO_UVLO_ENA_F

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::VCCIO_UVLO_ENA_F

[10] VCCIO_UVLO_LTC mask bit (reset 1)

◆ VDD_UVLO_ENA_F

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::VDD_UVLO_ENA_F

[8] VDD_UVLO_LTC mask bit (reset 1)

◆ VDDA_UVLO_ENA_F

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::VDDA_UVLO_ENA_F

[9] VDDA_UVLO_LTC mask bit (reset 1)

◆ VSA_UVLO_ENA_F

uint32_t TMC9660::SYS_CTRL::FAULT_INT_ENABLE::VSA_UVLO_ENA_F

[7] VSA_UVLO_LTC mask bit (reset 1)

The documentation for this struct was generated from the following file:

tmc9660_sys_ctrl.hpp

Public Attributes

Static Public Attributes